When Do We Need Non-Quasistatic CMOS RF

When do we need Non-Quasistatic CMOS RF-Models?
Elmar Gondro1 , Oskar Kowarik1 , Gerhard Knoblinger2 , and Peter Klein2
1
University of Bundeswehr,
Institute of Electronics, Werner-Heisenberg-Weg 39, D-85577 Neubiberg, Germany
2
Infineon Technologies AG,
Balanstraße 73, D-81541 München, Germany
Abstract
This paper presents criteria for the onset of NQS effects
derived from time transient device simulations and Sparameter measurements. For the first time it has been
proved that e.g. a 10 µm NMOS transistor can be described up to 27 MHz and a 0.2 µm device up to 46 GHz
by the quasistatic approach while the accuracy of the description of the inversion layer charge is still 99 %.
Technology Simulations
(TSupremTM )
Time Transient
Device Simulations
(MediciTM )
⇒ Qinv = Qinv (t)
DC-Measurements
AC-Measurements
⇒ S-Parameters
L = 0.2 . . . 10 µm
f = 0, 0.1 . . . 200 GHz
Introduction
Due to continuous down-scaling CMOS-technologies are
playing a more important role in RF systems. Therefore there is a strong demand for compact small signal
models describing accurately also the high-frequency region. An often mentioned problem hereby seem to be
non-quasistatic phenomena. In contrast to (1, 2, 3) this
paper will show, however, that their influence is often
over-estimated under small signal conditions.
The aim of this paper is to determine the transition between quasistatic and non-quasistatic effects in terms of
the frequency, the channel length and the applied voltages. Thus, it will be possible to estimate a theoretical
limit up to which quasistatic MOSFET models are reasonable.
Extraction of the
QS/NQS Transition
Fig. 1: Proceeding of our investigations.
According to AC considerations our work focuses on the
small variation of the inversion layer charge ∆Qinv (t)
(fig. 2). This contrasts to the normal approaches which
investigate the turn-on and turn-off behavior since the
large-signal channel build-up lasts much longer than its
reaction on small signal variations.
Fig. 1 summarizes our proceeding in a flowchart.
Device Simulations
Quasistatic Operation Assumption
The device behaves quasistatically as long as the terminal
voltages are varied slowly enough for the charge to follow
”immediately” at any position in the device. Then, these
charges can be assumed identical to those that would be
found if DC voltages were used instead (4). This can
be interpreted in the way that the NQS operation starts
as soon as the inertia of the charge carriers can not be
neglected any more.
As the transient behavior of the channel inversion layer
charge Qinv (t) can not be measured, we have performed
extensive device simulations (MediciTM ) in time transient mode. In order to stay as close as possible to
our measured device performance, we executed technology simulations (TSupremTM ) on a commercial quartermicron process as input for our device simulations.
As RF devices are mainly used for analog circuits, saturation is surely the most important operation region. There-
1111111111
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inversion layer
VGS ∼
L
00000000
11111111
111111111
000000000
000000000
111111111
00000000
11111111
00000000
11111111
000000000
111111111
pinch-off point
000000000
111111111
y
Qinv (VGS )
Qinv (VGS + ∆VGS )
n
∆Qinv (t) =
inv · sin (ωt + φ)
Q
p
a) VGS (t) [V]
1.51
VGS (t) = 1.5 V+0.01 V·sin (ωt)
1.5
1.49
b) Qinv (t) /q [1/µm]
4380
x
b inv /q
Q
4360
Qinv (1.5V)
q
f
fore the following investigations will focus on a typical AC 4300
operation point of
Qinv (1.49V)
q
π
1/2π
3/2π
0
to vary sinusoidally between its DC extremes of
inv (f → 0).
Qinv (1.5 V ± 0.01 V) = ±Q
Fig. 3 shows the frequency-normalized transient response
of the inversion charge Qinv (t) to the applied gate bias.
inv of the inversion layer charge decreases
The amplitude Q
with higher frequencies, and its phase shift φ increases.
Note, that the channel charge of a 0.25 µm MOSFET
varies only by about 60 carriers per µm width for a gate
voltage variation of 10 mV. Therefore very exact simulations were required.
To achieve a smooth sine wave and to include the nonlinearities of the devices, 256 time steps were needed for
each frequency and gate length simulation.
inv , φ) depending on the freThe characteristic values (Q
quency f and the gate length L can be seen in the fol inv of the inversion layer
lowing figures: the amplitude Q
charge (fig. 4) remains nearly constant up to a certain
frequency limit and then decreases steeply, whereas the
phase shift φ (fig. 5) varies linearly with the frequency.
From these figures we can extract a frequency limit fN QS
(figs. 6 and 7) that guarantees the desired accuracy.
2π
ωt [rad]
VDS = 2.5 V.
If we apply VGS (t) = 1.5 V + 0.01 V · sin (ωt) as time
transient AC gate voltage, we expect the total inversion
charge
L
inv · sin (ωt + φ)
Qinv (t) dx = Qinv,DC + Q
Qinv (t) =
binv (f →0)
Q
q
φ(Qinv )
Fig. 2: Scheme of inversion layer along the channel at 4340
different gate biases.
4320
VGS = 1.5 V ≈ (VCC − Vth ) /2 and
Qinv (1.51V)
q
f = 0.1 GHz
10 GHz
30 GHz
50 GHz
100 GHz
200 GHz
4400
Fig. 3: a) Applied gate voltage vs. time (VDS = 2.5 V)
for transient analysis with 256 time steps/period
b) Inversion layer charge of a MOSFET with
L = 0.25 µm (W = 1 µm) varying in amplitude
and phase according to the applied gate bias for
different frequencies.
inv (f → 0) [dB]
inv /Q
Q
0
−2
97 % = −0.26 dB
−4
−6
−8
−10
−12
0.01
L = 0.2 µm
0.25 µm
0.3 µm
0.4 µm
0.5 µm
1.0 µm
2.0 µm
5.0 µm
10.0 µm
0.1
L
QS
1
NQS
10
fN QS (97 %, L = 1 µm) = 5.3 GHz
100
f [GHz]
Fig. 4: Normalized inversion layer charge amplitude vs.
applied frequency (VGS = 1.5 V, VDS = 2.5 V,
W = 1 µm) in logarithmic scale for different gate
lengths.
φ (Qinv ) [◦ ]
0
We define the accuracy as the deviation of the magnitude
and phase of the inversion charge from their DC values
inv (f → 0) = Qinv (1.51V) − Qinv (1.50V) and
inv = Q
Q
φ (Qinv ) = 0.
Up to this frequency fN QS no effects on the small signal
parameters can be observed for a given gate length.
−12.0
−22.5
−45.0
QS
−67.5
0
The advantage of our strategy is a physics-based welldefined separation of the inner transistor from parasitic
effects (5, 6).
L = 0.2 µm
0.25 µm
0.3 µm
0.4 µm
0.5 µm
1.0 µm
2.0 µm
NQS 5.0 µm
10.0 µm
10
20
30
L
40
50
60
70
fN QS (−12 ◦ , L = 1 µm) = 6.0 GHz
80 90 100
f [GHz]
Fig. 5: Phase of the inversion layer charge vs. the applied
frequency for different gate lengths.
fN QS [GHz]
100
10
inv (f → 0) = 99.9 %
inv /Q
Q
99 %
97 %
1
required accuracy
simulated ft
measured ft
0.01
0.2
To verify our observations RF measurements on CMOS
finger structures (W = 96 µm) in quarter micron technology were performed. The small-signal scattering parameters (Sij ) have been corrected using a two-step deembedding technique with open and short structures (7).
In order to obtain a better relationship between our transient simulations and S-parameter measurements, the terminal currents have to be evaluated: the extracted unity
current gain frequencies ft = f (ID /IG ≡ 1) of different
devices show good agreement between our measurements
and simulations (fig. 8).
NQS
0.1
Measurements and Discussion
h21 = ID /IG [−]
100
QS
1
10
L [µm]
Fig. 6: Frequency limit fN QS derived from the decrease of
the charge amplitude vs. gate length in comparison
with ft .
fN QS [GHz]
100
L
10
measurement:
L = 0.25 µm
0.35 µm
0.50 µm
1.05 µm
1
φ (Qinv ) = −1 ◦◦
−2 ◦
−5
−12 ◦
10
simulation:
L = 0.2 µm
0.25 µm
0.3 µm
0.4 µm
0.5 µm
1.0 µm
2.0 µm
5.0 µm
10.0 µm
0.01
0.1
1
10
ft (L = 1 µm) = 5.1 GHz
50
f [GHz]
NQS
Fig. 8: Extraction of ft (L) from the unity current gain
(measurement and simulation).
1
accepted phase shift
0.1
simulated ft
measured ft
0.01
0.2
QS
1
10
L [µm]
Fig. 7: Frequency limit fN QS derived from the phase shift
of the charge vs. gate length in comparison with ft .
The measured phase shift ϑ of the current gain h21 =
ID /IG at ft remains constant over a wide range of operating points in the saturation region (fig. 9), proving that
our focus on simulating one typical operating point was
justified.
Taking into account that circuits can not be operated
inv and φ deviaabove ft , we were interested, which Q
∆ϑ(h21 ) at ft [◦ ]
90
Conclusion
W/L = 96/0.25
96/0.35
96/0.50
96/1.05
80
70
60
50
VGS = 0.7 V ≈ Vth +200 mV
40
VGS = 1.5 V
30
VGS = 2.5 V
20
10
0
10
20
VDS = 2.5 V
30
40
50
IDS [mA]
Fig. 9: Measured phase shift of the current gain h21 =
ID /IG at ft vs. operating points for different gate
length.
tions (figs. 6 and 7) have to be accepted for a desired
frequency range: fig. 10 quantifies the deviation from
inv (f → 0) = 1 and
inv /Q
the quasistatic assumption Q
φ (Qinv ) = 0, and thus shows, up to which frequencies
one can simulate quasistatically all gate lengths of the
analysed technology.
inv /Q
inv (f → 0) [%]
100 % − Q
6
φ (Qinv )
inv (f → 0)
inv /Q
−10 1 − Q
5
φ (Qinv ) [◦ ]
−12
−8
4
−6
3
−4
2
−2
1
0
0
0.2
0.4
0.6
0
1
fN QS /ft (L) [−]
0.8
Fig. 10: Trade-off between decreasing accuracy and increasing frequency: e.g. for simulating quasistatically transistors with arbitrary gate length up
to 1/2 ft a phase shift of −6 ◦ and an amplitude
accuracy of 99 % have to be accepted.
This paper presents criteria for the beginning of NQS effects. They depend on the applied frequency, the gate
length, and especially the required accuracy, whereas the
operation voltages turned out to be of minor importance.
Various devices of a commercial process with gate lengths
ranging from 0.2 to 10 µm have been investigated by time
transient device simulations and S-parameter measurements.
It has been proved that e.g. with an accuracy of 99 %
in the description of the inversion layer charge a 10 µm
NMOS transistor can be described up to 27 MHz and a
0.2 µm device up to 46 GHz by the quasistatic approach.
If we tolerate an accuracy in the amplitude of 96 % and in
the phase shift of −12 ◦ , one is able to describe the MOSFETs’ small signal behavior quasistatically up to ft (L)
for all gate lengths. Otherwise a NQS approach is required. To our knowledge this is the first time that such
numbers are reported.
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