Base Technological Solutions of «Basis.5» IMA Platform
Transcription
Base Technological Solutions of «Basis.5» IMA Platform
Base Technological Solutions of «Basis.5» IMA Platform Dmitriy Kulikov, Konstantin Tarandevich Base Requirements to “Basis.5” IMA Platform Resources sharing by several applications 1 2 3 4 5 6 7 8 9 10 11 12 13 Incremental certification Part number reduction Common toolset for different applications Module nomenclature minimization Increased number of supported functions Scalability OPEN technologies and high-speed switched fabric architectures High performance heterogeneous architectures Portable software Resources reconfigurability COTS technologies Tools and development processes integration General system solutions standardization 14 2 “Basis.5” IMA Platform Evolution IMA 1G Platform Architecture CPM C O R E 0 C O R E 1 C O R E 0 C O R E 1 CPM CPM CPM C O R E n C O R E 0 C O R E n C O R E 1 C O R E n C O R E 0 C O R E 1 C O R E n VPX VPX 6U 6U (VITA46,VITA48) Software Portability Implementation CPM CPM C O R E 0 C O R E 1 C O R E n C O R E 0 C O R E 1 CPM CPM C O R E n C O R E 0 C O R E 1 C O R E n C O R E 0 C O R E 1 C O R E n OPEN Embedded Computer Technologies and Standards Support, Platform High-Speed Switched Fabric Architecture and MultiCore Processor Module Architecture 3 “Basis.5” IMA Platform Evolution C O R E 1 CPM CPM CPM C O R E 0 C O R E n C O R E 0 C O R E 1 C O R E n C O R E 0 C O R E 1 CPM C O R E n C O R E 0 C O R E 1 C O R E n IMA 2G Platform Architecture Multilevel Reconfiguration of Computational Resources CPM C O R E 0 C O R E 1 C O R E 0 C O R E 1 CPM CPM CPM C O R E n C O R E n C O R E 0 C O R E 1 C O R E n C O R E 0 C O R E 1 Creation of Integrated Environment for Software Development C O R E n 4 “Basis.5” IMA Platform Prototype VPX 3U IMA 2G Platform (Resource Center Configuration) (VITA46,VITA48) CPM PMC/XMC (VITA20,VITA42) Central Processing Module GPMm Graphic Processor Mezzanine Module M3m NSM ARINC-664 Network Module Mass Memory Mezzanine Module AIMm Avionics Interface Mezzanine Module МСM IMA 2G Platform (IRDC Configuration) PMC/XMCMezzanine Carrier Module PSM Power Supply Module 5 Base System Solutions of “Basis.5” IMA Platform 6 Base Requirements to ARINC664p7 (AFDX) End System Jitter Redundancy Concept Integrity Checking Redundancy Management 7 Variants of ARINC664p7 (AFDX) End System Implementation HW Implementation on lowperformance systems Lack of flexibility at adaptation according to new requirements HW life cycle reduction Full recertification at substitution of HW implementation (element base) Development costs increase vs SW Higher requirements to system performance Problems of multicore solutions certification High level of adaptation to new requirements Scalability Low cost error correction Portability at HW substitution Incremental certification at modernization Possibility of COTS solutions usage at implementation Development costs and time reduction 8 ARINC664p7 (AFDX) End System Implementation in “Basis.5” IMA Platform HW/SW Structure of ARINC 664 (AFDX) End-System (AFDX ES) in CPM Implementation Features Jitter Timer core1 Integrity checking SW implementation according to ARINC664p7 requirements Redundancy management SW implementation according to ARINC664p7 requirements Intercommunication with ARINC653 OSRT Shared memory (RAM) or L2/L3 ARINC615A support Via intercommunication with CPM initial loader Configuration data original format XML Functional testing AIM company SW/HW test equipment 9 Functional Testing of ARINC664p7 (AFDX) End Device Researched Issues: The possibility of ARINC664p7 (AFDX) end system SW implementation according to the requirements of the standard ARINC664p7 (AFDX) end system SW implementation functioning on multicore CPU in combination with ARINC653 compatible RTOS The possibility of COTS solutions usage for application-specific interface creation The possibility of testing using HW/SW equipment and the methods of AFDX leading manufacturer 10 Implementation of ARINC664p7 (AFDX) End System Functional Testing 1/2 2/2 End System Functional Test Bench Structure 11 Results of Functional Testing of ARINC664p7 (AFDX) End Device SW Implementation Achieved Results: Creation of the effective ARINC664p7 (AFDX) end device SW implementation (0 < Jitter < 4 µs) The system is easily adaptive to new requirements and scalable Creation of portable SW components Adoption of test equipment of one of the leading AFDX devices manufacturer Correction of SW only during testing Usage of COTS solutions at the implementation Test Report with the detailed Test Protocol 12 13