Activités 65nm / 130nm - Indico

Transcription

Activités 65nm / 130nm
Marlon Barbero - CPPM
ATLAS-IN2P3
15 octobre 2013
Plan
• Question de la tenue aux radiations des pmos étroits en
65nm.
• Nouveaux tests sous irradiation.
• Organisation de l’activité au sein de RD53.
• Priorités ATLAS-France 65nm/130nm pour 2014.
Marlon Barbero CPPM, ATLAS-France 15 octobre 2013
2
Dose effects on Shift register
 Tests carried out on the ATPIX65 chip
 Small array of pixels 16x32
 Designed at Berkeley with the 65 nm
CMOS process
 PS tests : 24 GeV protons (SEU tests)
 At high levels of dose, failures appear
from 400 MRad in the shift register
Tests with 24 GeV proton beam
 SEU tolerant memory design for the
ATLAS pixel readout chip
 CERN Xray Tests : 10 keV
 The chip was placed to 1cm of the
source
Tests with Xray beam
 The dose rate is 6.24 Mrad/hour.
 A dose level of 950 Mrad reached after
one week and a half
 The same behavior as for the proton
tests
 DFF Failures appear from a dose level of
400 Mrad
3
CPPM’s previous studies
Rows 0-255
Rows 0-255
• Test SEU in LBNL-dvp’ed 65nm proto (CERN PS) 
Observed localized bits stuck in shift register used for pixel
config. loading.
390 MRad to 420 MRad
260 MRad to 310 MRad
• Hypothesis: TID effect /
Pattern 1111
Pattern 1111
leaking.
• Narrow pmos dose effect.
Columns 0-15
ATLAS-France – 65nm studies and RD53
Columns 0-15
4
Banc de test pour caractérisation de
transistors
Test board:
- 4 layers,
- class 4 (insulation min. 150µm)
- chip package LCC44 cts (not a good
idea)
- better in JLCC44
- delay: 12 days ( wait for it for the week
31)
- components already received
Supply for the commands of ESD
protections
Triaxial2coax connexions for
IV measurements (Vhigh,
Vlow)
KEITHLEY 2634B
(sourcemeter)
6
KEITHLEY 7002 (switches
matrix)
slots
available (Keithley
7158)
(each slot contains 10 inputs to 2
outputs)
GPIB links
NVDD, PVDD,
VSS
LabView
software
5
Etude d’effet de dose au CERN
• Irradiations sous X au CERN du 7 au 16
octobre  transistor pmos de petites
tailles ( tenue aux radiations des
librairies digitales?).
• Quelques problèmes techniques sur cartes
de test  véritable démarrage mercredi
matin.
• >700MRad en ce moment.
6
Ids (A)
Résultats 300MRad
D012 nmos :120nm/60nm (@Vds=50mV)
7 (V)
Vgs
Ids (A)
PD012 pmos :120nm/60nm (@Vds=50mV)
Vgs (V)
8
D024 nmos :240nm/60nm (@Vds=50mV)
Ids (A)
Ids (A)
Résultats 300MRad
PD024 pmos :240nm/60nm (@Vds=50mV)
Vgs (V)
Vgs (V)
• Maintenant: Finalisation d’irradiation  1GRad? Démarrage
de la période d’annealing.
• Bilan dans quelques semaines.
9
RD53
• Nouveau groupe de RD approuvé par LHCC (fin juin).
• “Development of Pixel Readout Integrated Circuits for
Extreme Rate and Radiation” == 65nm ATLAS / CMS.
• Période initiale de 3 ans.
• 2 spokemen: Christiansen (CERN/CMS) & Sciveres
(LBNL/ATLAS).
• Instituts: Bari / Bonn / CERN / CPPM / Fermilab / LBNL /
LPNHE / NiKHEF / New Mexico / Padovia / Pavia & Bergamo
/ Pisa / Perugia / PSI / RAL / UCSC / Torino (~100 auteurs)
• 6 Groupes de Travail / Thématiques:
– WG1: Radiation (qualification de la techno pour 1GRad / 1016
neq.cm-2, évaluation des librairies digitales après irradiation,
modèle transistors après radiation).
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RD53 -suite– WG2: Top Level Design (méthodologie, vérification -ASIC
contenant 0.5Gtrans!-, analog integration, power distrib., clock
distrib. etc…).
– WG3: Simulation Test Bench (system verilog simulation,
optimization -global/regional/pixel architecture, lien avec les
événements physiques…).
– WG4: I/O (interface definition, protocols, blocs de readout et de
contrôle…).
– WG5: Analog Design (évaluation de différents ampli / d’ADC
techniques -ToT, shared ADC…-).
– WG6: IP Blocks (definition des besoins, librairie de blocs IP,
s’accorder sur les specs communes, …).
• Groupes Français: CPPM (WG1-MB convener-/WG6) - LPNHE
(WG1/WG3/WG6) - LAL/Orsay (en cours d’approbation)
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LPNHE
RD53
LPNHE est engagé à participer à la
collaboration. Une attention particulière à la
possibilité d'utiliser des technologies telles
que les mémoires associatives pour le
formatage / compression des données
Tracking trigger upgrade ATLAS: FTK
LPNHE est impliqué dans le développement des
puces de mémoire associative 65 nm (leadership
en collaboration avec INFN)
2012/2013 – mini@sic prototype
2013/2014 – AMchip05: ~12 mm2 MPW prototype
2014/2015 – AMchip06: puce pour installation
finale de FTK
AIDA
LPNHE est impliqué dans la réalisation du
common blocks a 65 nm (WP3):
- readout logic blocks
- SET tolerant logic
Et dans les sub-projects (WP3):
- “Readout ASICs in 65nm technology
interconnected using the CEA-LETI or EMFT
process” (LAL/LAPP/LPNHE/MPP)
- “Interconnection of ATLAS FEI4 chips to
sensors using SLID interconnection and ICV
(high density TSVs) from EMFT”
(MPP/GLA/LAL/LIV/LPNHE)
mini@sic prototype
reçu en Juin,
en cours de test,
premiers résultats
très satisfaisants
LAL/OMEGA participation in RD53
LAL/OMEGA decided to joint RD53. Request to RD53 IB
was sent 16 september 2013
AIDA overlap: common blocks development (one block of
the list: ramp generator -pour ADC Wilkinson-, 10bit DAC,
analog probe buffer, PLL 40-500 Mhz)
Common work with CERN on IP blocks on-going
AIDA: 65 nm chip for EMFT(SLID) prototype to be
decided.
Request for 2014: 23 kEuros
Blocks CPPM
• SEU Tolerant Memories (physical node separation, TRL,
error correction….).
• Analog MUX + 10/12-bit DAC (avec designer LAPP Annecy).
• SAR ADC.
• Comparator.
• Pixel charge ADC (avec designer LPSC Grenoble).
• Bandgap Voltage Reference.
• Temperature Sensor.
14
65nm requests 2014
• CPPM:
– Design test transistors, blocks… – 23k
– Irradiation and tests – 10.5k
– Licences – 1.5K
• LAL: 23k.
– OmegaPix.
– Block dvp.
– puce 65nm pour EMFT (SLID).
• LPNHE: 15k.
– 5k production IC (au sein de RD-53???).
– 10k contribution pour puce OmegaPix.
15
Manpower
• LAL omega: A. Lounis, G. Martin-Chassard, D. Thienpont, J.
Tongbong.
• LPNHE: G. Calderini, M. Bomben, F. Crescioli (D), J.F. Genat
(D), O. Le Dortz (D), G. Marchiori.
• CPPM: P. Breugnon, M. Menouni (D), D. Fougeron (D), J. Liu
(PhD), M. Barbero, A. Rozanov, P. Pangaud (D), S. GodiotBasolo (D), A. Wang (D), F. Gensolen (D)
16
Résumé: en ce moment
• RD53  ATLAS + CMS ; organisation de / momentum pour
l’activité 65nm (CPPM / LPNHE / LAL impliqués).
• Premier but: Validation de la technologie 65nm aux doses du
futur HL-LHC.
• Pour le moment: Questions sur la tenue aux radiations des
pmos étroits en TSMC 65nm.
• Irradiation d’une ASIC de test sous rayons X.
• 2nd meeting RD53 WG1 la semaine prochaine.
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Conclusion
• Priorités 2014:
– Irradiations transistors 65nm TSMC Xray / protons (PS fin
2014???)  question de la tenue des librairies digitales.
– Irradiation autres technologies 65nm.
– Travail sur design blocks 65nm.
• Financement 2014:
– Demandes IN2P3: CPPM 35k / LAL 23k / LPNHE 15k.
– Comment utiliser l’argent d’Aida WP3.3? Seulement pour design
blocks? (caractérisation de transistor de tests??? matrices de
pixels???)
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backup
19
65nm irradiation (CPPM/Mohsine)
• Narrow PMOS dose effect.
20
SEU tolerant memory
A.Rozanov IN2P3 15.10.2013
ESD study
Bandgap reference
Generic ADC for monitoring
Temperature sensor
Sensors
• Probably different in different layers
• Planar, 3D, diamond – classical sensors
(realistic, but high costs of sensors and bumpbonding)
• CMOS sensors (HV CMOS, HR CMOS, T3
CMOS)
• In case of 2D MAPS 65nm design can be
reused for digital part
Pixels chip
• Building blocks: connection with AIDA, but specific
pixel specification
• Reliability, SEU tolerance
• High rate
• Large chip 2x2 cm, 1 billion transistors
• Complex: close to Pentium processor, 256K channels
of DAQ system per chip
• Low power (0.3 W/cm2)
• CERN frame contract with TSMC and IMEC, design tool
set, libraries, design exchange (including AIDA blocks)
Pixel chip generations
Generation
Current
FEI3, PSI46
Phase 1
FEI4, PSI46DIG
Phase 2
Pixel size
100x150um2 (CMS)
50x400um2 (ATLAS)
100x150um2 (CMS)
50x250um2 (ATLAS)
25x100um2 ?
Sensor
2D, ~300um
2D+3D (ATLAS)
2D (CMS)
2D, 3D, Diamond, MAPS ?
Chip size
7.5x10.5mm2 (ATLAS)
8x10mm2 (CMS)
20x20mm2 (ATLAS)
8x10mm2 (CMS)
> 20 x 20mm2
Transistors
1.3M (CMS)
3.5M (ATLAS)
87M (ATLAS)
~1G
Hit rate
100MHz/cm2
400MHz/cm2
1-2 GHz/cm2
Hit memory per chip
0.1Mb
1Mb
~16Mb
Trigger rate
100kHz
100KHz
200kHz - 1MHz
Trigger latency
2.5us (ATLAS)
3.2us (CMS)
2.5us (ATLAS)
3.2us (CMS)
6 - 20us
Readout rate
40Mb/s
320Mb/s
1-3Gb/s
Radiation
1MGy (100Mrad)
3.5MGy (350Mrad)
10MGy (1Grad)
Technology
250nm
130nm (ATLAS)
250 nm (CMS)
65nm
Architecture
Digital (ATLAS)
Analog (CMS)
Digital (ATLAS)
Analog (CMS)
Digital
Buffer location
EOC
Pixel (ATLAS)
EOC (CMS)
Pixel
Power
~1/4 W/cm2
~1/4 W/cm2
~1/4 W/cm2
3rd generation pixel architecture
•
•
•
95% digital (as FEI4)
Charge digitization
~256k pixel channels per chip
•
•
Pixel regions with buffering
Data compression in End Of Column
CPPM contributions to 65nm chip
• Test 65nm pixel matrix designed by Abder Mekaoui at
LBNL, pixel size 25x125 um, 3x4 mm, 16x32 pixels
• Pixel configuration: Triple Redounded Latch (TRL) 12.5µm ×
4.3µmwith error correction. Data loaded with shift register
(SR) DFF 6µm × 2.4µm
• Irradiation at Los Alamos, CERN PS (CPPM), X-ray CERN
(CPPM)
SEU test results
• DFF in Shift register
Pattern 0000 Pattern 1111
All
patterns
Pattern 0000 Pattern 1111
Rows 0-255
Rows 0-255
All
pattern
s
• TRL memory
Columns 015
Columns 015
Columns 015
Columns 0-15
Columns 0-15
Columns 0-15
SEU test results
• DFF 260-310 Mrad
• DFF 390-410 Mrad
Proton PS 24 GeV tests
• Test 16 columns of 256 TRL and 256 DFF. Design
from ARM standard library.
• σTRL = 2.6 10-16 cm²
• σDFF = 4.5 10-14 cm² σDFF / s TRL = 170
After 400 Mrads the state of
some DFF cells remain at 1
Narrow pmos dose effect
• High increase of the threshold voltage, transistor
completely off at 850MRad X-ray
39
40
Organization
• 17 institutes, 100 authors (50 designers)
• Two co-spokepersons: Maurice Garcia (ATLAS),
Jorgen Christiansen (CMS)
• Institutes Board
• Initial plan for 3 years
• May finish in common ATLAS-CMS chip, but
exchange of experience and blocks will already
big success
• Next IB 4 October 2013 at CERN after Aix-LesBain HL LHC workshop
Working groups
WG
Domain
WG1
Radiation test/qualification
Qualification of technology to 10 MGy TID, 1016 n.eq./cm2. Transistor simulation models after irradiation.
Evaluation of logic cell libraries after irradiation. Expertise on radiation effects in 65nm
WG2
Top level design
Design methodology, verification and test of ~5 × 108 transistor IC. Analog integration in large digital chip.
Power distribution Synthesis constraints. Clock distribution and optimization
WG3
Simulation and verification test bench
System Verilog simulation and Verification framework. Optimization of global architecture/pixel regions/pixel
External system and external physics data. Verification of test chips and evolving designs
WG4
I/O
Definition of readout and control interfaces (e.g. LPGBT). Definition of standardized I/O protocols and performance
Implementation of readout and control interface blocks. Standardized interfaces: Control, Readout, etc.
WG5
Analog design
Evaluate and compare alternate amplifier designs.
Evaluate and compare charge ADC techniques vs. number of bits (TOT, shared ADC, etc.)
WG6
IP blocks
Define common requirements for IP block design. Evaluate, document, and keep library of IP blocks
Generate overview and recommendations. Each block will have its own prototyping milestones
Participation matrix
Institute
WG1
Radiation
WG2
Top level
Bari
C
Bergamo-Pavia
A
Bonn
C
A
CERN
B(*)
CPPM
WG3
Sim./Ver
WG4
I/O
WG5
Analog
A
WG6
IPs
A
C
A
B
A
B
B
A
(*)
A
C(*)
A
B(*)
A
B
C
C
B
A
Fermilab
A
B
LBNL
B
A
B
LPNHE Paris
A
B
A
A
A
A
A
NIKHEF
New Mexico
A
Padova
A
Perugia
B
Pisa
PSI
RAL
B
A
A
A
A
B
B
A
A
A
B
A
C
B
B
Torino
C
B
C
UCSC
C
B
C
A: Core competency, B: High interest, C: Ability to help
B
A
A
A
A
C
A
A
A
(*): General CERN support for 65nm
Conclusions
• 3D Tezzaron-GF on hold due to financial constrains,
wait and see
• CMOS sensor RD on good track (chip 3D techno).
Potentially may bring very large cost saving and
increase in physics reach
• ATLAS and CMS give good example of cooperation in
order reduce costs by RD53 in technology 65 nm. Start
with TSMC, but radiation studies will be critical for final
choice.
• RD53 compatible with all sensors, including HV CMOS

Activités 65nm / 130nm - Indico

Transcription

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