Qualification of the CMS Barrel Pixel Detector Modules

Preprint typeset in JINST style - HYPER VERSION
Qualification of the CMS Barrel Pixel Detector
Modules
Sarah Dambach1,2 , Christina Eggel1,2 , Urs Langenegger1, Andrey Starodumov2 and
Peter Trüb1,2
1
Institute for Particle Physics, ETH Zurich, 8093 Zurich, Switzerland
Paul Scherrer Institute, 5232 Villigen PSI, Switzerland
E-mail: [email protected], [email protected], [email protected],
[email protected], [email protected]
2
A BSTRACT: To be written.
K EYWORDS : Particle tracking detectors, Detector alignment and calibration methods.
Contents
1.
Introduction
1.1 Barrel Detector Modules
1.2 Controls of the Readout Chip and the Token Bit Manager
1.3 Optimization Criteria
1.4 Test Setup
1
2
3
6
9
2.
Startup Tests and Threshold Measurements
2.1 Startup Tests
2.2 Threshold Measurements
10
10
11
3.
DAC Optimization, Tests, and Calibration
3.1 DAC Optimization
3.2 Functionality Tests
3.3 Performance Tests
3.4 Calibration Algorithms
12
12
16
18
21
4.
Production Results
4.1 Production
4.2 Verification of DAC Setting
27
27
27
5.
Test procedure
5.1 Test suite I (after assembly)
5.2 Test suite II (before mounting)
31
31
33
6.
Module grading
6.1 Pixel defects
6.2 Chip performance
6.3 Module sensor quality
6.4 Module production quality
6.5 Overall production quality
6.6 Summary of mounted modules
34
34
36
36
37
38
38
1. Introduction
The CMS experiment [1] is a general-purpose detector for the Large Hadron Collider at CERN. The
CMS tracking system consists of two subdetectors: the silicon pixel detector at the center of the
experiment and the silicon strip detector. The pixel detector comprises three barrel layers at radial
–1–
distances of 4.4 cm, 7.3 cm, and 10.2 cm from the beampipe and two forward disks at ±34.5 cm and
±46.5 cm longitudinal distance from the interaction point. The barrel part consists of 672 modules
and 96 half-modules, the forward part of 672 plaquettes.
The tracking system of the CMS experiment is designed to provide precise and efficient measurements of charged particle trajctories and the reconstruction of decay vertices of long-lived
particles. At the design luminosity of 1034 cm−2 s−1 on average about 1000 charged particles will
emerge from the interaction region every 25 ns. This environment requires a radiation-hard tracking
detector with high granularity and fast response.
The readout chips of the CMS tracking detectors are fabricated in standard 0.25 µ m CMOS
technology, which is inherently radiation hard due to thin gate oxide and special design rules. XXX
Also sensor radiation damage? XXX
To keep the occupancy at the innermost layers below 1%, a pixelated detector is required. With
a pixel size of 100 µ m × 150 µ m in the rφ × z directions the expected occupancy is at 10−4 in the
innermost layer. This low occupancy allows fast track finding at the high-level trigger.
In the barrel pixel detector, the drift of the electrons to the collecting pixel implant is perpendicular to the 3.8-T magnetic field. This results in a Lorentz drift spreading the charge over
several pixels. Charge interpolation of the analog readout signal provides a substantially improved
hit resolution compared to the single-pixel resolution.
This paper is organized as follows. First a short description of the pixel barrel detector modules
is provided, focusing on the aspects relevant for testing. In section 1.4 the test setup used for
module qualification is discussed. Section 3 provides the implementation details of the individual
tests performed in the course of module qualification, section 4 shows the results. The full test
suite performed for module qualification is described in section 5. The scheme for grading the
tested modules and the overall results for all barrel detector modules are given in section 6.
1.1 Barrel Detector Modules
The pixel barrel detector is built in a modular way and comprises 672 modules and 96 half-modules
with a total of 48× 106 pixels. A standard module has a size of 66.6 mm × 26 mm, and weighs 3.5 g,
and comprises 16 readout chips (ROC). Half-modules, necessary to combine the two detector half
shells without gap, contain 8 ROC.
The barrel modules are built out of the following components (see Fig. 1). The silicon sensor
with a thickness of 285 µ m is micro-bumpbonded to the ROC by means of indium bumps with a
diameter of about 20 µ m [2], connecting each sensor pixel with a pixel unit cell (PUC) on the ROC.
The sensor is covered by a High Density Interconnect (HDI), distributing signals and voltages to
the ROC, and serving as an interface to the front end electronics. The connection is established
over two cables: (i) a power cable for supply and bias voltages and (ii) a Kapton multi-channel
signal cable for the control signals and the analog readout. The Token Bit Manager (TBM) chip on
the HDI organises the readout of all ROC. The base strips beneath the ROC provide the necessary
mechanical rigidity and are used to mount the module onto the support structure. On the detector
up to 12 modules will form a Control Network.
The purpose of the ROC [13] is to measure the charge produced in the sensor, amplify it, compare it to an adjustable threshold, store it during the latency of the L1 trigger, and finally to send its
amplitude in zero-suppressed mode over an optical readout chain to the off-detector analog-digital
–2–
a)
b)
Figure 1. (a) Exploded view of a pixel barrel module. The components, from top to bottom, are: signal
cable, power cable, HDI, silicon sensor, 16 ROC and base strips. (b) Photograph of a pixel barrel module.
converters. Its amplitude will be referred to as ‘pulse height’ (PH). The ROC consists of three main
building blocks: 4160 pixel unit cells, 26 double column peripheries, and one control and interface
block. The 4160 pixels are arranged in 52 columns and 80 rows in z and rφ , respectively. The
readout is organized using the column drain mechanism [?], one token arranges the readout of two
neighboring columns (called double column).
1.2 Controls of the Readout Chip and the Token Bit Manager
A schematic view of the readout chain in the ROC is shown in Fig. 2. The module characteristics
and performance are controlled by 26 digital-analog converters (DAC) and 3 registers on the ROC
and three DAC on the TBM. The DAC on a ROC can be separated into two main categories: (i)
DAC set to the same value on all ROC. While some of them are not used, the majority has been
set to optimal values that do not differ from ROC to ROC. (ii) DAC adjusted for every single
ROC. Both types of DAC are now introduced in their order along the readout chain. The detailed
discussion of DAC optimization will follow in section 3.
The DAC Vleak_comp is used to compensate for a possible leakage current in the sensor. At
the startup of the experiment the leakage current is expected to be small, and this DAC is set to 0.
A ROC-internal charge injection signal can be used to simulate deposited charge in the sensor.
Its amplitude is controlled through Vcal, an 8-bit DAC with a high and low range setting. In the
former one unit of Vcal corresponds to ≈ 65 electrons, in the latter to about ≈ 455 electrons (see
section 3.4 for the calibration of these values). If not mentioned otherwise, Vcal will be given in
high range DAC units. The DAC CalDel delays the charge injection with respect to the ROC clock,
one unit in CalDel corresponds to XXX ns.
The two 4-bit DAC VrgPr and VrgSh and the two 8-bit DAC VwllPr and VwllSh control the
preamplifier and shaper system; they are intended to be set to identical values, respectively. Figure 3a) shows the timewalk as a function of these four DAC. Here timewalk refers to the time
difference of signals of different amplitude crossing the threshold. XXX Determination of timewalk XXX Figure 3b) shows the PH as a function of VhldDel for different values of VwllSh =
VwllPr. Small DAC settings correspond to small timewalk, but also to small signal amplitudes.
The 8-bit DAC VhldDel controls the sampling point of the signal amplitude. The 8-bit DAC Vhld-
–3–
Figure 2. Schematic view of the readout chain inside the readout chip.
Del should be set so that the signal is sampled at its maximum value independent of its size, i.e., the
timewalk should be minimal. Since the timewalk should be minimized and the PH maximized, an
optimum was determined as VrgPr=VrgSh=0 and VwllPr=VwllSh=35. Figure 3c) shows the PH as
a function of VhldDel for different low-range Vcal settings. The amplitude decrease for high Vcal
settings is due to saturation in the readout chain XXX. A value VhldDel=160 is consistent with the
–4–
requirements above.
a)
b)
c)
Figure 3. (a) Timewalk as a function of the preamplifier and shaper DAC. For each measurement,
VrgPr=VrgSh and VwllPr=VwllSh. (b) Pulse height (PH) as a function of VhldDel and VwllSh = VwllPr. (c)
PH as a function of VhldDel for different Vcal values.
The threshold is set for the entire ROC with the DAC (VthrComp). Four trim bits allow a
threshold modification per pixel (scaled with Vtrim). These DAC depend on the desired threshold
and have to determined for each ROC and pixel.
After the PUC the signal is sent to the double column periphery where an offset can be added
with VoffsetOp and the 4-bit DAC Vbias_sf. The two DAC have overlapping functionalities, and
since VoffsetOp is optimized (see section 3.1), Vbias_sf =10 is fixed.
XXX In a final step the signal level can be shifted (VIbiasOp, controlled by VIon and VOffsetRO, controlled by VIbiasOp) and—in the control and interface block—scaled (VIbias_PH).
XXX There is an almost binary influence of the 8-bit DAC VIbiasOp on the PH: below VIbiasOp ≈ 20 no signal is seen independent of the amount of injected charge, while above this value
the PH shape does not change. Therefore the setting can be done more or less arbitrarily, VIbiasOp = 50 was chosen. The 8-bit DAC VIon has a stretching influence on the PH. Since the pulse
height range will be adjusted by VIbias_PH, it is set in the intermediate region: VIon = 130.
The readout of all pixels is organized in two sequences: (i) a fast step (the signal passing
through the comparator) to store the time of a hit and (2) a slow step (the signal passing through
the sample and hold mechanism) to read the signal amplitude and the pixel address (column and
row). For the first path every pixel on a double column sends a current to the periphery, its intensity
–5–
is adjustable by VIColOr. If more than one pixel was hit in a double column at the same time the
currents are added. In the periphery a timestamp is created and stored in a time-stamp buffer. The
second step is to read out the addresses and the signals stored in the sample and hold capacitances
and to assign them to the corresponding time stamp.
The 8-bit DAC VIColOr adjusts the amount of current which will be sent to the periphery. If
the ROC is operated in the self triggering mode, a threshold on the number of hit pixels per double
double column can be set. It is therefore important to know how large the current per pixel is. Since
the self-triggering mode will not be used, the only concern is to have a current large enough that a
hit pixel will be recognized, which is fulfilled for settings of VIColOr > 20; the default setting is
at VIColOr = 99.
The pixel address is sent from the PUC to the periphery as digital current levels and converted
there into digital voltage levels. The threshold of this conversion is adjusted by the 8-bit DAC
VIbias_bus, set to VIbias_bus=30.
In the control and interface block the address levels can be shifted (Ibias_DAC) before they
are prepended to the analog signal. Together they can be scaled (VIbias_roc) and will be sent out
from the control and interface block.
The 8-bit DAC VIbias_roc stretches the address levels and, likeVIbias_PH, the PH. Since
VIbias_PH is optimized, VIbias_roc is set close to its maximum to keep maximal flexibility in
adjustments.
Different voltages have to be distributed over the ROC. Vdig and Vana determine the digital
and analog voltages used in various ROC locations, VComp regulates the supply voltage of the
comparator, and Vsf of the sample and hold circuit. Vdig is a 4-bit DAC and is used to regulate
the digital voltage on the ROC. Since it does not affect the PH its only constraint is its influence
on the address levels. It is set to 6, a value where the amplifier shows a linear behavior and the
ROC-voltage is below the external voltage (2.5 V). The 4-bit DAC VComp regulates the comparator
supply voltage. In the intermediate region of its possible range the comparator already works very
reliably. Therefore it is set to 10. Irradiation may require that it has to be adjusted.
VNpix and VSumCol are designed for adjusting the minimum number of hit pixels in a double column and the minimum number of double columns in the self-triggering mode of the pixel
detector. Since this possibility will not be used, both of these 8-bit DACs are set to 0.
The TBM [4] is controlled via three DAC. Dacgain stretches the digital TBM levels, Inputbias and Outputbias stretch both, the signals of the ROCs and and the TBM. Due to the high track
density in the two inner layers of the barrel the TBM consists of of two parts with identical functionality. Normally only one half is used for controlling a module (single mode). In the two inner
layers of the barrel detector the TBM is operated in the dual mode, each half controlling 8 ROC.
Both Inputbias and Outputbias are 8-bit TBM DACs which have no influence on the PH if
they are above a certain threshold (around 110). Both are set above this threshold to 128.
All DACs are listed and sorted by category in Table 1.
1.3 Optimization Criteria
Before describing the algorithms developed to optimize the performance of the ROC the possible
optimization criteria and figures of merit are discussed. On the one hand, a reliable operation with
minimal power consumption, yet maximum signal amplitude and minimal time walk, are criteria
–6–
Table 1. DAC and registers of the pixel modules. PUC refers to the pixel unit cell, CIB is the control and
interface block, and the TBM is the token bit manager. DAC names in italic font indicate 4-bit DAC, DAC
names in roman font indicate 8-bit DAC.
Voltage regulators
PUC: Analog
Trigger
Calibrate
Periphery
CIB
Registers
TBM
Vana, Vdig, Vcomp, Vsf
Vleak_comp, VwllPr, VrgPr, VwllSh, VrgSh, Vtrim, VthrComp, VhldDel
VIColOr, Vnpix, VSumCol
VCal, CalDel
VIbias_bus, Vbias_sf, VoffsetOp, VIbiasOp, VOffsetRO, VIon
Ibias_DAC, VIbias_PH, VIbias_roc
CtrlReg, WBC, RangeTemp
Inputbias, Outputbias, Dacgain
quantifiable in the laboratory. On the other hand, parameters influencing the position resolution
(determined from an ensemble of tracks) need to be validated through a detailed simulation and
can be optimized only indirectly.
The module readout is zero-supressed, i.e., only the PH and address of hit pixels are sent in
analog form to the front end electronics. An illustrative example of a readout is shown in Fig. 4. The
first eight clock cycles form the TBM header, followed by the readout of all ROC and terminated
by the TBM trailer. The TBM header starts with three Ultra Black (UB) levels. An UB is a low
level marking the lower bound of the analog signal range. The three UB are followed by a black
(B) level defining the zero level of the differential analog signal. The four remaining clock cycles
encode an 8-bit event number. The minimal readout of each ROC starts with an UB, a B, and a
level called “last DAC”. This level displays the value to which the last addressed DAC was set, or
the value of the temperature sensor. Each hit adds a block of six clock cycles to the analog readout,
encoding the double-column (2 cycles) and row (3 cycles) of the hit pixel, and the pulse height (1
cycle). The addresses are encoded as digital signals on six levels. The readout is terminated by the
TBM trailer, containing two UB, two B, and four clock cycles with the TBM status information.
The analog readout is digitized in 12-bit ADC off the detector. To exploit maximally the available
ADC range, the PH range should cover the same maximal range as the address levels. As the B
level is the zero line, the range should be symmetric with respect to the B level.
As the position resolution is mostly affected by the linearity of the PH in the low range, we
dicuss now the quantification of the signal linearity. Figure 4b) illustrates a typical PH as a function
of Vcal. For Vcal between 0 and 10 the signal is below the threshold of the comparator and no
signal is visible. For 10 < Vcal < 50 the PH is very non-linear. This implies that the conversion of
a specific PH (here around -700) to deposited charge is no possible (see section ?? for a discussion
of the influence on the position resolution). For 50 < Vcal < 125 the pulse height behaves linearly,
above 125 it starts to saturate. This saturation does not pose a problem for position resolution since
this corresponds to more than twice the minimum ionization charge.
To quantify the amount of non-linearity in the lower Vcal range a hyperbolic tangent function
is fitted to the PH:
PH = p3 + p2 tanh(p0Vcal − p1 )
(1.1)
–7–
a)
b)
Figure 4. a) Output of a module with one pixel activated on ROC 0. The initial eight cycles encode the TBM
header, the following 6 show a single pixel hit on ROC 0, followed by 15 ROC without hit, and terminated
by 8 cycles of the TB< trailer. b) Analog pulse height (PH) vs. Vcal
The relevant parameter of this fit is p1 , which shifts the curve in the Vcal direction and can be used
as a quantification of the non-linearity of the PH curve in the lower range. The smaller p1 is, the
more linear the PH curve is in the low range.
a)
b)
c)
Figure 5. Illustrations of aspects of signal linearity. Low-range linearity quantified with a tanh fit and pixel
response considered a) linear and b) non-linear. c) Linearity in the full range.
Figure 5 illustrates that values of p1 ≈ 1 imply a PH curve with a very linear behavior down
to low Vcal values, while p1 ≈ 2.5 means saturation in the low Vcal range. From visual inspection
a value of p1 ≤ 1.4 was chosen as target for the linearity, optimized through the DAC Vsf and
balanced against the digital power consumption, as described in more detail in section 3.
In addition to the linear behavior in the lower Vcal range, the linearity over a large part of the
Vcal range and the full use of the entire available ADC range is important. To quantify this aspect,
a polynom of 5th degree is fitted to the PH curve and the tangent through the inflection point in the
main region is determined. Starting from the inflection point in both directions, the PH-difference
between the tangent and the fit is calculated. By definition, the linear range is determined as the
region where this difference is smaller than 10% of the total pulse height range. The figure of
merit is defined by a quadratic addition of the linear part in Vcal direction and the linear part in PH
direction as shown in Figure 5c:
linear range =
q
(∆Vcal )2 + (∆PH)2 .
–8–
(1.2)
1.4 Test Setup
The testing of all barrel pixel detector modules was performed at Paul Scherrer-Institute (PSI) with
the testing hardware setup described in this section.
A desktop PC with a Scientific Linux 4 (SLC4) installation is the central control unit of the
test setup. It is connected through USB cables to four electronics test-boards, specifically designed
at PSI for testing the barrel pixel modules. Each test-board provides the necessary supply voltages
and electrical signals (clock, trigger, readout, . . . ) for one module. To analyse the readout of the
module, each test-board includes two 12-bit ADC sampling the analog signal in the interval [-2048,
+2047], with 1 ADC unit corresponding to 0.128 mV. The central control unit of the test-board is
formed by a field-programmable gate array (FPGA) with an embedded processor. XXX Each module is connected through a module adapter board to its test-board. A Keithley high-voltage supply
XXX provides the bias voltage (nominally 150 V, but ranging up to 600 V for leakage current tests)
for the test-boards; one single output is fanned out to all four test-boards. The four modules are
housed in a custom-built temperature-controlled box (TCB). The TCB allows a rapid temperature
cycling at a well-defined humidity.
All code and testing algorithms are implemented in a standalone C++ software package running under SLC4. For data storage and analysis the ROOT framework [5] is used. Fig. 6 shows
an unified markup language diagram of the most important classes. The attributes and operations
shown are only typical examples of the complete lists of variables and methods. Likewise the two
test classes “Trim” and “IVCurve” serve as examples for the large number of implemented test
classes. Furthermore, classes like those for the graphical user interface, the command line, the
logging functionality, etc. are omitted for clarity.
The core of the test classes consists of the six classes ControlNetwork, Module, ROC, TBM,
DoubleColumn, and Pixel, representing the corresponding hardware entities. They reproduce their
functionality like setting a DAC or enabling a pixel. These commands are sent to the test-board
represented by the class TBInterface. The DoubleColumn and Pixel classes do not directly communicate with the test-board. All their commands require the specification of the ROC-ID, therefore
they are processed via the ROC class. The TBInterface class itself makes use of the class USBInterface to send its commands to the (physical) test-board (at an earlier stage another interface was
used for the communication between PC and test-board). The Test class provides common code
to the derived test classes like Trim or IVCurve. An example for this common code is the function ModuleAction which loops over all ROC on a module and executes the test algorithm for this
ROC. If this behaviour is not suitable for a derived class, as for instance in IVCurve, the derived
class replaces it with its own code. The IVCurve uses the class Keithley to communicate with the
high-voltage supply.
The presence of the FPGA processor allows the execution of parts of the test algorithms directly on the testboard. This speeds up the tests by reducing the data transfer between PC and
test-board. Especially interactive algorithms, where the test flow depends on the results of previous measurements, as is the case for threshold measurements benefit substantially. Table 2 shows
a comparison of the duration of some test algorithms with and without running parts of the code
directly in the FPGA. Without the FPGA processor the full test time would be longer by a factor of
about three.
–9–
ControlNetwork
modules
GetModule
1
Module
hubID
DigitalCurrent
1
Test
testParameters
ModuleAction
16
TBM
tbmParameters
SetRegister
ROC
dacParameters
rocID
SetDAC
TBInterface
tbParameters
SendCal
DoubleColumn
doubleColumn
EnableDoubleColumn
Trim
vcal
AdjustVtrim
IVCurve
voltageStep
ModuleAction
26
Keithley
port
SetVoltage
160
USBInterface
buffer
Write
Read
Pixel
trimbit
EnablePixel
Figure 6. UML diagram of the most important classes of the C++ testing software.
Table 2. Test duration of different algorithms with and without running parts of the code directly in the
FPGA. Remove this table XXX?
Test duration per ROC [s]
Trim Bits Test
Bump Bonding Test
Noise Measurements
Trimming
Pulse Height Calibration
PC based code
145
80
210
450
245
FPGA based code
26
20
89
156
20
2. Startup Tests and Threshold Measurements
This section discusses the low-level tests needed to ensure the basic functionality of the ROC and
TBM. The threshold measurements are ingredients in most of the tests described in section 3.
2.1 Startup Tests
The current test Provided by CE (?) xxx
– 10 –
The data trigger level (DTL) test determines the threshold below which an UB level is measured on the test-board. If the test-board detects three signal below this level, they will be interpreted as the UB levels of the TBM header and the ADC starts the sampling of the analog readout.
It stops after detecting two signals below the DTL. The DTL is adjusted in the following way:
First the DTL starting at zero is decreased until a valid analog readout is measured. Once this is
achieved, the UB level is determined and the final DTL is set 100 ADC units above this value.
The DAC-programming test is a simple check that all DAC of each ROC can be programmed:
For each ROC the Vcal DAC is set to its extreme values 0 and 255 and the change of the “last
DAC” is determined. If it lies below 20 ADC values, the ROC is considered to be defective.
The TBM test checks the basic functionalities of both TBM channels. For both the communication is probed by reading out the event number. A second test concerns the readout mode of the
TBM. The TBM can be read out in a single mode, in which the readout of all ROCs is sent to one
analog channel. This is the default test mode and will be used for the modules in the third layer
of the detector. In the dual mode, one half of the ROC is read out via the first analog channel, the
other half via the second channel. This will be the readout mode of the modules in the first two
barrel layers. The TBM test ensures that the module can be successfully operated in both modes
by checking the length (i.e. the number of ROCs) of an empty readout.
Before starting the other tests, the sampling point of the analog signal is optimized by adding a
delay to the module clock with respect to the ADC clock. The sampling point is set to the center of
the range, in which the pulse height is not more than 20 ADC units apart from the maximal value.
The Pixel Readout
To generate and read out a hit in a pixel, the following sequence of actions has to be taken: (1)
Enable the double column of the corresponding pixel; (2) Enable the calibrate injection to the
pixel; (3) Enable the readout of the pixel; (4) Send a calibrate signal to the module; (5) Send a
trigger signal to the module. In the following the term “to read out a pixel” always refers to this
procedure.
2.2 Threshold Measurements
The threshold of a pixel can be measured in different ways. One possibility is to keep the threshold
defined by the VthrComp DAC fixed and to find the Vcal value, at which a pixels start to respond.
This kind of threshold will be called “Vcal-threshold”. The second possibility is to inject a signal
with a fixed amplitude defined by the Vcal DAC and to find the VhtrComp value, at which this
signal is above threshold. This threshold is referred to as “VthrComp-threshold”.
Usually this measurement is done by reading out the hits in a fixed bunch crossing. This type
of threshold is called ‘in-time’ threshold. If a pixel has e.g. an in-time Vcal threshold of 60, this
does not necessarily mean, that the pixel does not respond for Vcal values lower than 60. It only
means that in the given bunch crossing no hits with lower Vcal values are registered. It is well
possible, that by reading out the previous bunch crossing, signals with lower amplitudes can be
observed. If a timing-independent threshold is required, the thresholds in different bunch crossings
have to be measured. The minimum of all these thresholds is called the ‘absolute’ threshold. If not
mentioned otherwise, a threshold determination usually refers to an in-time Vcal-threshold.
– 11 –
The concrete measurement of a threshold proceeds in the following way. In a first step the
considered DAC is varied in steps of 4 DAC units starting from one end of the DAC range. For
each value the pixel is read out once. As soon as the response of the pixel changes, the scan stops
and the current DAC value is returned. In a second step the threshold curve starting from this rough
estimate of the threshold is measured with several readouts per pixels in steps of 1 DAC unit. If
the readout efficiency reaches 50% the corresponding DAC value is returned. Due to the step size
of 1 DAC value and the limited number of readouts, the precision of this measurement is 1.3 DAC
values for 5 readouts per point. Since this threshold measurement has to be executed almost one
million times per module during all tests, a more precise measurement by fitting the threshold curve
is only done for the noise measurement (see below).
3. DAC Optimization, Tests, and Calibration
3.1 DAC Optimization
Several DACs on the ROC have a big influence on its behavior, for example on the functionality
or on the pulse height linearity. Their best setting varies quite much from ROC to ROC. Therefor
they are dynamically adjusted for every single ROC.
Dacgain
The TBM 8-bit DAC Dacgain only has an influence on the analog levels of the TBM. Therefore it
is the ideal candidate to set the ultrablack level of the TBM to a user-defined value, −1000 here.
It is adjusted in such a way that the ultrablacks of both channels of the TBM differ least from the
goal value, but lie below it. Since the position of the different levels is summetric around the black
level and can not be shifted but only be stretched, this also fixes the position of all other levels, in
particular the one of the highest TBM level to +1000 in this case.
Ibias_DAC
Ibias_DAC is an 8-bit DAC and has similar to Dacgain almost only an influence on the ROC levels.
The little shifting influence on the pulse height can be ignored since this will be adjusted anyway
in a later step. It is used to set the ultrablack of all ROCs to the same value as the TBM ultrablack.
In the same way as for the TBM this also fixes the position of the ROC address levels. Ibias_DAC
can be set upto a precision of 0.73 DAC units.
Vana
The 8-bit DAC Vana is set in such a way that the analog current drawn per ROC is 24 mA. The
dependency of the analog current on Vana is shown in Figure 7. It can be set upto a precision of
0.55 DAC units.
VthrComp versus CalDel
All ROCs only work in a specific region of the VthrComp - CalDel range. To measure this region
Vcal is set to 200 in low range DAC units (was found to be a good setting for many tests in [7]),
five calibrate signals are sent for each pair of VthrComp and CalDel, and the number of readouts
– 12 –
Figure 7. Dependency of the analog current on Vana
is counted. Since the working range does not change very strongly from pixel to pixel on the same
ROC, this procedure is only done for one single pixel. A typical shape of the valid readout area is
shown in Figure 8.
Figure 8. Procedure of finding a stable working point in the VthrComp - CalDel space
The used pair of the two DACs should lie as far away as possible from the the edges of the
readout area. To find such a point in a first step the minimal value of VthrComp where a signal
appears (horizontal line in Figure 8) is searched. From this point one goes up 50 VthrComp units
and searches for the CalDel value in the middle of the readout range. This pair of the two DACs
is defined as working point for calibration purpose. For the trimming of a ROC, VthrComp will be
set in a different way. CalDel can be set upto a precision of 0.53 DAC units.
VIbias_PH
An important criterion of the DAC optimization is that the pulse heights and digital levels of all
ROCs lay inside the same ADC range. In case of the levels this goal is already reached by setting
the TBM and ROC ultrablack levels to a specific value. The only adjustment remaining is the one
of the pulse heights, which should fill the goal ADC range. The general idea behind this procedure
– 13 –
is first to stretch or squeeze the pulse height range with one DAC and shift it afterwards to the
desired region.
As shown in Figure 9 with the 8-bit DAC VIbias_PH the complete pulse height curve can be
stretched. Since this DAC has no influence on any address levels at all it is the optimal candidate
to stretch or squeeze the size of the pulse height range to the favored one, 2000 (from −1000 to
+1000) in this case. VIbias_PH can be set upto a precision of 2.62 DAC units.
Figure 9. Influence of VIbias_PH on the pulse height curve
Two DACs which only shift the pulse height curve and also have no influence on any address
levels at all are VoffsetOp and VOffsetR0. Since they are correlated, they first will be discussed
before coming back to the adjustment of the pulse height range.
VoffsetOp versus VOffsetR0
VoffsetOp and VOffsetR0 are both 8-bit DACs which shift the pulse height curve and therefore have
an influence on the linear range. The correlation between them is shown in Figure 10. It can be seen
that for VOffsetR0 > 100 any linear range can be achieved by setting VoffsetOp correctly. Because
of temperature and pixel to pixel variations of this behavior VOffsetR0 is set to 120 and VoffsetOp
is adjusted afterwards. It can be set upto a precision of 0.41 DAC units.
While the absolute value of the pulse height range is already adjusted with VIbias_PH, VoffsetOp can now be used to shift the pulse height curve in the goal ADC range. Since the variation of
VoffsetOp also influences the pulse height range a little bit and VIbias_PH has a small influence on
the position inside the ADC range, the procedure of adjusting those DACs needs to be repeated on
average three times.
Vsf
The 8-bit DAC Vsf is the crucial DAC to get a linear behavior of the pulse height in the low Vcal
range. The higher it is the more linear the pulse height curve gets, what is shown in Figure 11.
The only problem is that the digital current of the ROC rises with increasing Vsf. Its absolute value
depends on the difference between Vana and Vsf, whereas the former is already adjusted and will
not be changed at this point anymore. The total digital current of a module as a function of Vsf of
one ROC is shown in Figure 12.
– 14 –
Figure 10. High range linearity in dependency of VoffsetOp and VOffsetR0
Figure 11. Influence of Vsf on the linearity
of a pixel
Figure 12. Influence of Vsf on the digital
current of a module, Vana fixed
The value of Vsf where the current starts to rise significantly is very chip dependent because
Vana also varies from ROC to ROC. Beside the dependency on Vsf the linearity of the pulse height
curve strongly depends on the temperature.
As shown in Section ?? the (non-) linearity of a pixel can be quantified by fitting its pulse
height curve with a hyperbolic tangent function. The parameter p1 of this fit is an indication for
the linearity. To adjust Vsf it is increased in steps of five until this parameter is smaller than 1.4; if
the increase of the digital current between Vsf = 0 and the recent setting is below 5 µ A this setting
will be used, otherwise Vsf will be lowered until the current increase is smaller.
This optimization is done for an average pixel in terms of linearity. Vsf can be set upto a
precision of 0.9 DAC units, while for time comsuming reasons it is set in steps of.
VthrComp versus Vtrim
The optimization of the 8-bit DACs Vtrim and VthrComp is part of the trimming which is described
in Section 3.4
– 15 –
3.2 Functionality Tests
Pixel Readout Test
In the first part of this test, the functionality of the mask bit is checked. By enabling the mask bit of
a pixel, the comparator in the PUC is disabled (cf. Fig. 2), therebye suppressing all hits in this pixel.
This functionality is very important, since a noisy pixel can prevent a whole double-column from
working properly by filling up the buffers in the double-column periphery. The mask mechanism
is checked by enabling the mask bit and trying to read out the pixel. If a pixel hit is generated, the
mask bit is defective.
In the second part of the test, it is verified that sending a calibrate pulse to the enabled pixel,
results in the corresponding hit information in the analog signal. For this, the pixel is read out 10
times with Vcal set to a value of 200 in the low range. If the hit does not show up in the analog
signal all ten times, the pixel is called “dead”. Before this test the VthrComp and CalDel DACs
have to properly adjust as described in 3.1.
Trim Bits Test
# Pixels
To individually adjust the thresholds of the pixels, each PUC stores four trim bits. By setting them
appropriately the pixel threshold is lowered by an amount depending on the Vtrim DAC value. In
the default untrimmed state, all trim bits are enabled, the corresponding trim value is 15. Disabling
single trim bits will lower the pixel threshold. To test whether all four bits work as expected, the
threshold is first measured in the untrimmed state. Afterwards all trim bits are enabled one after
another and each time it is checked, that the threshold has decreases with respect to the untrimmed
threshold. If the threshold difference is less than 2 DAC values, the trim bit is considered as
defective. Figure 13 shows the threshold difference distributions for a ROC with no defects. For all
pixels the threshold decreased by more than 10 DAC units. The Vtrim values used for the different
trim bits are listed in Table 3.
Trim value 14
3
Trim value 13
10
Trim value 11
Trim value 7
102
10
1
0
10
20
30
40
50
60
∆ Threshold
Figure 13. Distributions of the threshold difference between untrimmed and trimmed pixels. For each of
the curve one trim bit was disabled.
– 16 –
Table 3. Vtrim values used in the trim bit test.
Trim value
15
14
13
11
7
Vtrim DAC
0
250
200
150
100
Address Decoding
# Pixels
An individual pixel address consists of five clock cycles in the analog signal: two cycles encode
the column index and three the row index [6]. Each clock cycle can take six different levels (c.f.
Fig 4). To correctly decode the pixel address, these levels have to be well separated. To check this,
the levels of all pixels in a ROC are measured and overlaid in a histogram as shown in Fig. 14. In
this histogram, a simple algorithm searches for separated peaks. If exactly six of them have been
found, the decoding limits are placed in the centres between two neighbouring peaks. These limits
are used in the second part of the test, which records the analog readout of each pixel and checks
whether the pixel generates the address which corresponds to its physical position on the ROC.
3
10
102
10
1
-400
-200
0
200
400
600
800
1000 1200
Analogue output level [ADC]
Figure 14. Address-levels of all pixels in a ROC. The dashed lines are the separation limits used for the
decoding of the pixel addresses.
Bump Bonding Test
An indium bump bond process for silicon pixel detectors has been developed at PSI [2]. To test
the bump bonding quality, a fast algorithm using the possibility to send a calibrate signal through
the sensor was devised [7]. The calibrate signal can either be injected directly to the preamplifier
(using switch 1 in Fig. 15) or to a pad on the ROC surface (using switch 2 in Fig. 15). Choosing the
– 17 –
second option, the calibrate signal induces a charge in the sensor, which mimics a hit in the sensor
pixel. Ideally, this hit is detected if the bump bond is present and not if the bump bond is missing.
This ideal situation is deteriorated in two ways. Occasionally the bump bond is not completely
missing but only has a poor connection to the sensor or the ROC. Even worse, for large enough
amplitudes a hit is triggered although the bump is missing. These hits are supposed to originate
from x-talk via a parasitic coupling between the calibration voltage line and the preamplifier.
Based on this experience, the following algorithm was developed, to check the bump bonding
quality. First the Vcal-threshold for the signal injection through the sensor is determined. Second
the threshold for the parasitic x-talk is measured (i.e. with both switches open). The difference of
the two thresholds (both measured in the high Vcal range) allows for a good discrimination between
bonded and unbonded pixels. If the bump bond is missing, both thresholds are more or less equal,
otherwise the difference amounts to −10 to −20 DAC units. It is found that the discrimination
between good and bad bump bonds is better the higher the threshold (i.e. the lower the VthrComp
value). This is made use of by setting the VthrComp DAC to a value, which is as low as possible,
but still large enough in order to detect the pixel response due to the x-talk.
The procedure has been validated by applying it to several specially prepared ROCs with
sensors, from which a few bumps were removed manually before bump bonding. Fig. 16 shows
the distribution of the threshold difference from which all missing bump bonds can be successfully
identified. From the experience of many module tests, a bump bond was defined to be bad, if the
threshold difference is larger than −5 DAC units.
Figure 15. Sketch of the PUC components relevant for the bump bonding test.
3.3 Performance Tests
Noise Measurements
To identify noisy pixels, which potentially have to be masked, the noise of each single pixel is
measured. The noise is determined by measuring the so called S-curve, which is the response
– 18 –
0
70
-5
60
50
-10
40
30
∆Threshold [DAC units]
row
80
-15
20
10
-20
0
0
10
20
30
40
50
column
# Pixels
(a)
3
10
good bumps
bad bumps
102
10
1
-25
-20
-15
-10
-5
0
5
∆ Threshold [DAC units]
(b)
Figure 16. Result of the bump bonding test for a ROC with known bump bonding defects. Figure (a) shows
a map of the threshold difference to check the correct identification of the bad bump bonds. Figure (b) shows
the threshold difference distribution, pixels with defective bump bonds are shown in red, good bump bonds
are plotted in green. All pixels with missing bumps could be identified.
efficiency of the pixel as a function of the amplitude of the calibrate signal. For an ideal pixel
without any noise, this would be a simple step-function: zero efficiency below the signal threshold
and full efficiency above. The effect of the noise is to smear out this step function. If the noise is
assumed to be Gaussian, the S-curve has the shape of an error function, with a width proportional
to the noise. A fast threshold scan provides a rough value for the threshold. In a window around
this value the S-curve is measured with high precision, i.e. 50 readouts per point.
The measurement is complicated by the fact, that the voltage of the calibration signal is not a
monotonous function of Vcal. There are a few cases, where a higher Vcal DAC value corresponds
to a lower voltage. The calibration voltage was measured as a function of Vcal for one ROC. This
measurement is used to plot the efficiency directly as a function of the calibration voltage. These
data points are then fit with an error function and the width and the position of the 50% point are
extracted, see Fig. 17. The width is first converted to Vcal DAC units (1 Vcal DAC = 1.20 mV)
and afterwards to electrons (1 Vcal DAC = 65 e− ). With this procedure, the noise of a pixel can be
– 19 –
Efficiency
determined with a precision of 13 e− .
1
0.8
0.6
0.4
0.2
0
0.095
0.1
0.105
0.11 0.115
0.12
0.125 0.13 0.135
Calibration voltage [V]
Figure 17. S-curve fit with an error function to determin the noise of a pixel.
Alternatively the noise can be determined from the pulse height measurement. For a fixed
signal amplitude, the pulse height is measured 1000 times and the RMS of the resulting distribution
is computed. Since other sources like the ADC, also contribute to the width of the distribution, the
RMS of the black level distribution is measured and quadratically subtracted from the pulse height
RMS. To compare the resulting number with the result from the S-curve method, it has to be
converted into a charge. This is done with the help of the pulse height gain. Up to a mean offset of
20 e− a good agreement between the two methods is found, therebye confirming that the S-curve
width originates from the noise. Fig. 18 shows the result of both measurements for the same ROC.
The edge pixel have a higher noise level due to their bigger size.
Sensor IV-curve
Defects in the silicon sensor are most easily found by measuring its leaking current as a function
of the applied bias voltage. Problems with scratches or spikes would show up as breakdown at
voltages below 100 V [8]. Since the sensor will be operated at voltages up to 600 V, the highvoltage is varied from 0 V to 600 V in steps of 5 V. The measurement of the leakage current is
performed 5 s after the voltage has been set. The error on the current measurement estimated from
repeated measurements of the same module is 2.1 · 10−3 µ A. The algorithm stops, if the voltage is
either at 600 V or the leakage current exceeds 100 µ A. The latter happens for many modules, but
this is not considered as a problem if the breakdown voltage is above 200 V, since the behaviour of
the sensor is expected to improve with irradiation. A typical sensor IV-curve of a good module is
shown in Fig. 19.
– 20 –
80
200
190
70
180
180
60
60
170
50
170
50
160
40
150
160
40
140
30
150
140
30
130
130
20
20
120
10
0
0
NoisePH
190
Row
200
70
NoiseSC
Row
80
120
10
110
10
20
30
40
50
Column
100
110
0
0
10
# Pixels
(a) S-curve noise
20
30
40
50
Column
100
(b) Pulse height noise
Entries
Mean
RMS
140
120
4160
23.55
13.88
100
80
60
40
20
0
-40
-20
0
20
40
60
80
100
NoisePH - NoiseSC
(c) Noise difference
Leakage current [A]
Figure 18. Pixel noise measured with two different methods: From the width of the S-curve (a), from the
pulse height scattering (b), and the difference of the two methods (c).
-5
10
-6
10
10-7
-8
10
0
100
200
300
400
500
Voltage [V]
Figure 19. Sensor IV-curve of a typical module at -10◦C.
3.4 Calibration Algorithms
Trimming
Due to variations in the electronic components, each pixel has a slightly different threshold. To
– 21 –
220
250
200
180
200
160
140
150
120
100
100
80
Vcal threshold [DAC units]
Vtrim [DAC units]
achieve a uniform threshold for all pixels, the trim bits of each pixel have to be programmed to a
suitable value. To do this, the trimming algorithm described below was developed.
The only input parameter to the trim algorithm is the threshold (in Vcal units) to which the
response of all pixels should be unified to. The three degrees of freedom which have to be properly
adjusted are the VthrComp DAC, the Vtrim DAC , and the trim bit value of each pixel.VthrComp
sets the global threshold for the ROC and Vtrim determines, how much the trim bits lower this
threshold. The influence of VthrComp and Vtrim on the threshold can be inferred from Fig. 20.
60
50
40
20
0
0
20
40
60
80
100
120
VthrComp [DAC units]
0
Figure 20. Vcal threshold of a pixel with all trim bits disabled as a function of VthrComp and Vtrim. Within
the white area no threshold could be determined.
The first step is to find the value of the VthrComp DAC which corresponds to the chosen
threshold in Vcal units. This is done by measuring for each pixel its VthrComp-threshold. As for
all other threshold measurements of the trim algorithm, the timing independent absolute threshold
is measured. Since the thresholds can only be lowered afterwards, the minimum value of this
distribution determines the global VthrComp value (a low VthrComp value corresponds to a high
threshold). This value is used during the rest of the algorithm. As can be seen from Fig. 20 there
is a maximal VthrComp value above which the ROC is not functional any longer. It turns out, that
this limit has almost the same value for all pixels. In order to operate not too close to this limit, it
is ensured, that the chosen VthrComp value is at least 10 DAC values apart from this upper limit.
The second step of the trim algorithm is to determine an appropriate Vtrim value. To find this,
the Vcal thresholds of all pixels are measured. The pixel which has the highest threshold is used
to determine the necessary Vtrim value. For this pixel the trim value is set to zero and Vtrim is
increased, until the threshold of the pixel is at the same level as the target threshold.
The third step of the trim algorithm consists in setting the trim bits for all pixels. This is done
by a binary search for the trim value, which gives a threshold as close as possible to the target
threshold. The search starts with a trim value of 7 and comprises four iterations. At the end, all
thresholds are measured once again to validate the procedure.
For a not too low target threshold, the trim values fill the whole range from 0 (maximally
– 22 –
# Pixels
trimmed) up to 15 (not trimmed). The presence of the upper VthrComp limit poses a problem,
when trimming for very low threshold is aimed for. In this case, the VthrComp DAC can not be
set as high as desired in step one. This is compensated by a higher Vtrim value in step two, but at
the price of a trim value distribution, which does not make use of the full available range. The trim
value distributions after the trimming to thresholds equal to Vcal 20 and 60 are shown in Fig. 21.
For the former threshold the trim values fill only the range from 0 to 12, therebye rendering the
threshold distribution more coarse.
3
Vcal 20
10
Vcall 60
102
10
1
0
2
4
6
8
10
12
14
16
Trim value
Figure 21. Trim value distribution after trimming to thresholds corresponding to Vcal 20 and 60. In the
former case the trim values do not cover the full range, due to the upper VthrComp limit.
With the final system it is not be possible to run highly interactive algorithms as the trim algorithms described above, because the detector control and readout systems (the FEC and FED) are
separated. A solution to this problem is to use the trim parameters measured during the module
qualification in the laboratory. During this procedure each ROC is trimmed to a threshold corresponding to 60 Vcal DAC units. It turns out that it is possible to extrapolate these trim parameters
to any other threshold by parametrising them as a function of the threshold [10]. To obtain these
parametrizations the trim algorithm was run for different thresholds. It is found, that VthrComp
and Vtrim depend linearly on the threshold. The trim bits do not change significantly with the
threshold. From the average of 16 ROCs the following parametrization was deduced:
VthrComp(thr) = VthrComp(60) − 0.65 · (thr − 60)
Vtrim(thr) = Vtrim(60) − 0.45 · (thr − 60)
trimbits(thr) = trimbits(60)
To validate the procedure, this parametrization was applied to a ROC and the resulting thresholds were measured, see Fig. 22. The measured thresholds deviate only little from the target thresholds. The widths of the threshold distributions are only slightly larger than those obtained by the
full trim algorithm.
– 23 –
Measured Threshold [Vcal]
65
60
55
50
45
40
35
30
25
30
35
40
45
50
55
60
Target Threshold [Vcal]
Figure 22. Validation of the parametrized trimming. The trim settings were extrapolated from the results of
the trim algorithm for a threshold corresponding to a Vcal value equal to 60. The plot shows the measured
threshold versus the target threshold using the parametrization described in the text.
Pulse Height Calibration
For the pulse height calibration on pixel after abother in read out. The Vcal DAC values for which
the pulse heights are measured are the following: 50, 100, 150, 200, 250 in the low Vcal range and
30, 50, 70, 90, 200 in the high Vcal range. In order to measure the pulse height for the low Vcal
values, the threshold and the timing of the injected signal have to adjusted as described in 3.1. To
increase the accuracy, each pulse height measurement is an average over 10 readouts.
In the offline part of the algorithm the points are fit with two different functions. First the
central points (the 10 points without the highest and the lowest points) are fit with a straight line.
The slope of this curve determines the gain and the Vcal value corresponding to zero pulse height
the pedestal. These values are measured with an accuracy of 1.5 · 10−2 ADC/DAC for the gain and
2.7 · 102 e− for the pedestal. Second the whole curve is fit with a hyperbolic tangent function to
quantify the nonlinearity for very low pulses.
The ROC has a built-in temperature sensor [6]. The temperature is measured by comparing
a temperature dependent voltage to a temperature independent reference voltage. The amplified
voltage difference is sent to the “last DAC ” signal of the analog output. To extract the voltage
difference from the measured ADC value of the “last DAC ”, the output signal has to be calibrated.
This can be done by using the ROC ability to send a known voltage difference to the “last DAC
”. Having measured the voltage difference at two different temperatures and assuming a linear
dependency, an absolute temperature measurement is possible.
The sensor is designed to measure temperatures in the range from −30◦ C to +70◦ C. To get
a better accuracy of the measurement, the reference voltage (to which the temperature dependent
voltage is compared to) can be programmed to be one of eight predefined voltages in the range
399.5 mV to 564 mV. The voltage difference used for the “last DAC ” calibration can also be chosen
among eight different values from −94 mV to +70.5 mV. For simplicity the calibration algorithm
– 24 –
measures in total all 16 numbers, whereof at the end only 2 are actually used for the calibration.
The temperature sensor voltage is measured with an accuracy of 0.56 mV.
Vcal Calibration
-
Most probable ionisation charge [e ]
In 2005 the first barrel modules underwent a test-beam at PSI (Villigen) with a 300 MeV pion
beam [11]. The results indicated, that the same Vcal value might correspond to different injected
ionization charges for different ROCs. If the beam hits the module e.g. at a right angle, the particles traverse 285 µ m of silicon and the ionization charge distribution is well described by a Landau
distribution with a most probable value of 21680 e− [9]. It was observed, that the position of this
Landau peak in terms of Vcal DAC units varied between ROCs. From runs at different angles, the
ionization charge can be extracted as a function of the Vcal DAC. Fig. 23 shows that the ionization
charge shows a linear dependency on the Vcal DAC. Astonishingly Vcal equal to 0 does not correspond to zero charge. The mean slope of the 13 ROCs shown in Fig. 23 is 61.1 e− /Vcal with a
RMS of 5.5.
30000
25000
20000
15000
10000
5000
0
0
50
100
150
200
250
300
350
400
Vcal [DAC units]
Figure 23. Ionization charge as a function of the Vcal DAC for 13 ROCs. The points have been extracted
from the position of the Landau peak in the test-beam 2005 data.
The Vcal calibration was repeated in the laboratory with the help of a variable energy X-ray
source. The test setup is shown in Fig. 24. The hit rate is highest for the central ROCs (zone 2) and
lowest for the ROCs on both ends of the module (zone 0). The used source consists of a primary
Americium-241 source, which excites characteristic X-rays from one of six possible targets (Cu,
Rb, Mo, Ag, Ba, Tb). The targets used for the calibration are barium, silver and molybdenum,
which produce between five and nine thousand electron-hole pairs in silicon (see Tab. 4).
The Vcal value, to which these charges correspond to, is determined in the following way.
First, for each ROC the threshold curve is measured by varying VthrComp. For each value, the
fully enabled module is randomly read out several thousand times and the number of hits in each
ROC is determined. To increase the probability to find a hit, the corresponding bunch crossing
is artificially stretched by stopping the clock sent to the module. The resulting threshold curve is
– 25 –
fit with an error function and the 50% point gives the VthrComp value of the corresponding line.
The VthrComp DAC is set to this value, and for each pixel its Vcal threshold is measured. The
mean of the resulting distribution gives the sought-after Vcal value. This procedure is repeated for
the different targets and the resulting points in the ionization charge vs. Vcal plane are fit with a
straight line.
Figure 24. Setup of the X-ray test.
Table 4. Targets used to produce secondary X-rays of specific energy. Listed are the X-ray energy, the
number of produced electron-hole pairs in silicon as well as the photon yield.
Target
Mo
Ag
Ba
Energy [keV]
17.44
22.10
32.06
Ion. charge in Si [e− ]
4844
6139
8906
Photon yield [s−1 sr−1 ]
2.43 · 104
3.85 · 104
4.65 · 104
For most of the modules the calibration was done with only two lines (silver and molybdenum)
due to the limited testing time available. A more precise calibration with three lines was performed
for a small subset of all modules. Table 5 shows a comparison of the different parameters of the
two test procedures.
Table 5. Comparison of the two-line and the three-line measurements.
Measured lines
Tested modules
Test duration
Triggers per VthrComp step
Bunch crossing length
– 26 –
2 lines
Mo, Ag
806
15 min
30000
25 µ s
3 lines
Mo, Ag, Ba
69
1h
5000
1.6 ms
The uncertainty of the measurements was estimated by repeated tests of one module. The
precision of the measurements strongly depends on the ROC position on the module. Table 6
shows the precision with which the slope of the calibration curve can be determined.
Table 6. Uncertainty of the slope determination for the measurement with 2 and 3 lines.
Zone 0
Zone 1
Zone 2
2 lines
15.6
7.6
5.8
3 lines
1.2
1.1
0.6
4. Production Results
4.1 Production
4.2 Verification of DAC Setting
For checking that all the optimizations are really successful one can investigate various criteria. On
the one hand on different ROC specific parameters but on the other hand also on reconstruction
specific parameters, especially position resolutions. The latter ones are taken from a CMSSW
simulation.
P1 Distributions
Figure 25 shows the distribution of p1 before and after the optimization of Vsf. Almost all nonlinear pixels are removed, the pixels are no longer more linear than needed, and the distribution is
much more uniform. The influence of the optimization on the digital current is shown in Figure 26.
The total digital current is only increased by 40 mA or 9%.
3
# modules
# ROCs
×10
8000
Entries 53338140
Mean 1.28
Entries 44528846
Mean 1.17
7000
6000
180
140
120
5000
100
4000
80
3000
60
2000
40
1000
20
0
-1
Entries 347
Mean 0.44
Entries 620
Mean 0.48
160
-0.5
0
0.5
1
1.5
2
2.5
3
3.5
4
p1
Figure 25. Distribution of p1 before and
after its optimization
0
0.3
0.35
0.4
0.45
0.5
0.55
Figure 26. Distribution of the digital currents per module before and after the optimization of p1
– 27 –
0.6
Digital Current [V]
ADC Range Utilization
To verify that the complete output of a ROC lies within the goal ADC range from −1000 to +1000
Figure 27 shows the output of a single ROC where one pixel is activated. Sequentially the ultrablack, the black, the last DAC, and the five address levels are shown. The last bin contains the
minimal and maximal value the pulse height can reach. It can be seen that both, the address levels
and the pulse height fill the complete goal ADC range.
1
1500
0.9
ADC value
2000
0.8
1000
0.7
500
0.6
0
0.5
-500
0.4
0.3
-1000
0.2
-1500
-20000
0.1
1
2
3
4
5
6
7
8
9
0
clock cycle
Figure 27. Output of a single ROC, including the minimal and maximal pulse height
Position Resolutions
To investigate the influence of the non-linearity a simulation using CMSSW_1_2_0 is done. 10000 muons
with a transverse momentum of pt = 10 GeV are generated in two ranges of pseudorapidity, 0.1 <η <0.1 (central barrel region) and 1.8 <η <2.0 (forward barrel region). For both ranges the
same pixel response is applied to all pixels, once a linear response and once a non-linear response.
Both the linear and the non-linear response are reconstructed with a linear and an area tangent
hyperbolic function. Afterwards a comparison between different combinations of responses and
calibrations in rϕ - and z-direction of layer one is done. Also the central and the forward barrel
region are compared.
Influence of the Responses and Calibrations To compare the resolutions for different responses
and calibrations one has to look separately on different η -ranges since the cluster shapes depend on
the pseudorapidity. In the central barrel region (-0.1 <η <0.1) the tracks pass the detector layers
almost perpendicularly while in the forward barrel region (1.8 <η <2.0) only under a few degrees.
1. Central Barrel Region
(a) Rϕ -direction:
The resolutions of the four combinations of linear and non-linear responses and calibrations and the corresponding deteriorations are shown in Figure 28. It clearly can be
seen that for a linear pixel one only gains 1.2 µ m in the resolution using an area tangent
– 28 –
hyperbolic calibration with four parameters instead of a linear one with only two parameters. If one instead uses a non-linear pixel the resolution becomes more than 50 %
worse for both calibration functions. Therefore it is very important to have all pixels as
linear as possible, independent on the used calibration function.
Figure 28. Position resolution in rϕ -direction in the central region of the pixel barrel detector
# pixels
(b) Z-direction:
In z-direction the resolution does neither depend on the response nor on the calibration.
The distribution in Figure 29 shows a non-gaussian shape because only a single was hit
and there is no Lorentz drift in z-direction.
400
350
300
250
200
150
100
50
0
-500
-400 -300 -200 -100
0
100
200
300
400
500
position resolution [µm]
Figure 29. Position resolution in z-direction in the central region of the pixel barrel detector
2. Forward Barrel Region
In the forward barrel region the resolution is around 7 µ m in rϕ - and around 23 µ in zdirection. It does neither depend on the response nor on the calibration but is a bit better than
in the central barrel region.
– 29 –
Table 7. Cluster sizes in the central and forward barrel regions with the RMS of their distributions
-0.1 < η < 0.1
1.8 < η < 2.0
2.0 ± 0.7
1.2 ± 0.6
2.1 ± 2.2
2.3 ± 1.0
6.0 ± 1.9
7.1 ± 2.8
rϕ
z
total
Influence of the Pseudorapidity Range To investigate the differences between the resolutions
in the central and the forward barrel region one simulates a binary pixel response. The resolution
in rϕ -direction is 21 µ m in the central and 7 µ m in the forward barrel region. The value in the
central barrel region is roughly as big as expected, the one in the forward direction is much better
then expected and comparable to the one with a linear response and area tangent hyperbolic reconstruction. This shows - together with the fact that resolution in the central and the forward barrel
region differ so much - that the resolution in forward direction is dominated by the shape of the
hit clusters, which are longish there. It is influenced by the length of the cluster and by the ratio
between the number of hit pixels in two rows. To certify this conclusion Table 7 shows the cluster
size in the two considered pseudorapidity ranges.
position resolution [µ m]
Influence of the Trimming The influence of the trimming quality on the position resolution is
also investigated. Therefore the threshold in the CMSSW simulation is set to the nominal value
of 2500 electrons and smeared by a gaussian distribution centered at 0 and characterized by the
width σ ; the noise is switched off in the simulation. Figure 30 shows the position resolutions in the
forward barrel region in rϕ - and z-direction as a function of threshold uncertainty σ . For realistic
values of the order of a few hundred electrons no influence on the position resolution can be seen.
This is also true for the central barrel region. A little influence is only seen in the forward barrel
region and z-direction for the completely unrealistic threshold uncertainty of 2500 electrons.
40
35
30
25
20
z-resolution
15
rϕ-resolution
10
5
0
0
500
1000
1500
2000
2500
threshold uncertainty [electrons]
Figure 30. Influence of the threshold uncertainty on the position resolution in the forward barrel region
Influence of the Uniformity of the Calibration In the last step of investigating various influences on the position resolution different responses of all the pixels are applied. To use realistic
– 30 –
Table 8. Position resolution for ideally uniform and for realisticly distributed pixel responses
Central Barrel Region
uniform
realistic
degradation
rϕ
z
9.76 µ m 15.94 µ m 6.18 µ m 63%
36.53 µ m 36.31 µ m -0.22 µ m -1%
Forward Barrel Region
uniform
realistic
degradation
rϕ
z
7.13 µ m
22.41 µ m
9.43 µ m
33.85 µ m
2.30 µ m
11.44 µ
32%
51%
results, measurements from the module testing [7] are used. The pulse height curves of about
25 million pixels are fitted with Equation (1.1) and the average values and deviations of all four
fit parameters are extracted. In the simulation of the pixels a response according to those values is
used, while in the calibration the average value is used in the area tangent hyperbolic function. The
results are shown in Table 8.
It can be seen that a per ROC instead of a per pixel calibration causes - except for the zdirection in the central barrel region - a big degradation of the resolution.
5. Test procedure
In this section, the full test suite for the modules of the BPIX will be described. The grading criteria
will be explained in section 6 and the module production quality will be summarized in section
6.4.
From module assembly to final mounting each module was thoroughly tested and calibrated.
In a first extensive test suite all modules were tested and graded. Before mounting the qualified
modules onto the detector half-shells, their functionality was rechecked and an x-ray test was performed.
5.1 Test suite I (after assembly)
In the standard test set-up, four modules were tested simultaneously in the cooling box of the test
station. At the beginning of the test suite, a data trigger level scan was performed. Modules with
less than four consecutive read-outs of length 64 were disabled. The test suite consisted of three
testing parts and one thermal cycling part, executed in the following order:
• standard test at −10◦C
• thermal cycling
• standard test at −10◦C, I-V curve measurement
• standard test at +17◦C, I-V curve measurement
– 31 –
The standard test comprises all functionality and performance tests, as well as calibration and
characterization of the module. It was performed in parallel for all four modules and is described
in section 5.1. The thermal cycling process lasted about one hour, during which the modules were
cycled ten times from −10◦C to 17◦C. The I-V curve was measured consecutively for each module
at two different temperatures, as described in section 5.1. To avoid running into the compliance
of the power supply, the leakage current of each module was checked after changing to a new
temperature first. Modules with a leakage current above 25 µ A at the operating voltage of 150 V
were disabled. Figure 31 shows the temperature profile and testing steps during a complete test
suite. As shown in figure 32 a) the initial test duration of about 10 was reduced to about 6 hours,
after optimising the thermal cycling and the time consuming I-V curve measurements.
Figure 31. Temperature profile of a full test suite
Standard test
The standard test can be divided into four main steps:
• Pretest to set ROCs into operating regime (analog current, ultra-black levels and threshold/timing settings)
• Functionality test of pixel readout circuits and electrical connections to sensor pixels (pixel
response, bump bonding quality, trim bit test and address decoding)
• Performance (noise) and calibration (pulse height calibration, trimming) of the ROCs
– 32 –
Figure 32. Test duration of a) standard test, b) reduced test (withtout x-ray calibration)
FIXME: description of FullTest
I-V curve
The measurement of the sensor leakage current versus reverse depletion voltage (I-V curve) was
performed twice after thermal cycling, once at −10◦C and once at 17◦C. The leakage current was
measured starting from 0 V up to 600 V in steps of 5 V. The measurement was stopped when the
leakage current exceeded 100 µ A.
5.2 Test suite II (before mounting)
Before mounting the modules onto the detector half-shells, their functionality and performance was
rechecked and an x-ray calibration test was performed. Figure 32 shows the test duration without
the x-ray calibration. Altogether this second test suite lasted about three hours and consisted of the
following steps:
• reduced test at −10◦C
• reduced test at 17◦C
• x-ray calibration
Reduced test
In the reduced test, some basic functionality tests were performed again and in addition it featured
the DAC optimisation for the pulse height calibration. It can be divided into the following steps:
• Pretest to set ROCs into operating regime
• Functionality test of pixel readout circuits
• Pulse height calibration including DAC optimisation
– linear range (Vsf, VhldDel ?)
– 33 –
– readout range (VOffsetOP, VOffsetRO ?)
– time walk (Vana) - removed!
FIXME: description of ShortTest
X-ray calibration
In order to describe the correlation of the Vcal DAC and the ionisation charge, the modules were
irradiated at a test station using a Molybdenum and a Barium x-ray source.
6. Module grading
The grading system for modules comprises the three categories A, B and C. Modules with grade A
have no or only minor defects. They can be mounted without hesitation. Modules with grade B are
of lesser quality than modules with grade A, but are still working acceptably well. Preferably these
modules ought to be put on one of the outer layers. Modules with grade C are seriously flawed or
not working at all. If all attempts to recuperate such a module failed, the final grade was left at C
and the module was considered to be waste.
The qualification criteria can be divided into three sections: pixel defects, chip performance
and the sensor leakage current of the module. The details of each are explained in the following
sections.
6.1 Pixel defects
Functionality
As part of the standard test, the readout circuits and the electrical connection to the sensor pixel
are tested for each pixel during Test Suite I. A pixel is counted as defective, if one or several of the
following tests failed:
• Pixel test (including test for mask defects)
• Bump-bonding test
• Trim bit test
• Address decoding test
In the pixel test, one checks that the pixel responds to a sequence of internal calibration signals.
The first calibration signal is sent while the pixel is disabled (masked). If a masked pixel responds
nevertheless, this is called a mask defect.
Performance
Based on the data collected during module testing, further pixel defects with respect to the performance of the pixels were introduced. In addition to the pixel defects listed in section 6.1, a pixel
will be counted as defective if
– 34 –
• the pixel is noisy (above 400 e) or shows a strange noise behaviour (below 50 e)
• the pixel could not be trimmed to a threshold of Vcal 60, i.e. a pixel with threshold below 50
DAC or above 70 DAC
• if the linear fit of the pulse height curve failed, i.e. the gain is below 1.0 ADC/DAC
• if the pixel saturated in the low Vcal range, i.e. parameter p1 of the hyperbolic tangent fit to
the pulse height curve is above 1.5
These criteria are based on Fig. 33 and 34. As shown in Fig. 34 b), a criteria to identify
misbehaving pixels based on the pedestal, cannot be defined.
Figure 33. Distribution of a) noise and b) trimmed threshold of pixels (all tested modules).
Figure 34. Distribution of a) gains and b) pedestals of pixels (all tested modules).
Grading scheme
The sum of all defective pixels on a ROC was added up and the module was graded according to
table 9. A mask defect however, is considered to be a serious defect: Being able to mask a noisy
pixel is crucial, as such a pixel may flood the readout system. Thus a module with as much as one
mask defect was already graded as C.
– 35 –
Table 9. Grading based on pixel defects
Grade
Defects / chip
Mask defects
A
≤ 1%
-
B
≤ 4%
-
C
> 4%
≥1
6.2 Chip performance
As described in [?] missing charge has an impact on the hit resolution. The charge information
depends on the pixel threshold and on the pulse height calibration. In case of a calibration based
on the average per double column or even per chip, the variation of gains and pedestals on a
chip should be limited. To ensure a uniform response of all pixels on a chip, restrictions were
also applied to the average noise and the width of the trimmed threshold. The initial choice of
performance based grading criteria was mainly determined from [?], and is shown in table 10.
These criteria were validated later on with the results from module testing.
Noise
The limit for the mean noise on a ROC was set to be 5 σ off the threshold. The threshold will be
set to 2000 - 2500 electrons for non-irradiated modules. Therefore the mean noise level should not
exceed 400 - 500 electrons.
Trimming
In order to unify the physical thresholds of all pixels on a readout chip, the global chip threshold
can be fine-tuned for each pixel by the use of four trim bits. After trimming, the RMS of the pixel
threshold distribution should not exceed 200 electons.
Pulse height calibration
The correlation of the pulse height and the amplitude of an injected calibration signal can be described by a linear function over a large range. The slope of this function is called the gain, and the
offset is called the pedestal. The relative gain width is calculated by dividing the RMS of the gain
distribution by the mean. The pedestal spread was converted into electrons by using the calibration
from the test-beam
σPed [e] = σPed [V cal DAC] ∗
65 e
[V cal DAC]
The spread in both parameters is acceptable if the mis-calibration contribution to the track and
vertex recontruction is less than the effects of multiple scattering. The tolerable variation of the
gains is about 20 % - 40 % and the pedestal spread can be as large as 1000 - 2000 electrons.
6.3 Module sensor quality
I-V curve
To detect eventual sensor damage during assembly, the limits were defined as shown in table 11.
The leakage current at the initial operational voltage of 150 V should not exceed 150 µ A. With
– 36 –
Table 10. Grading based on chip performance
Grading scheme
Grade
e−
Noise in
Relative Gain Width
Pedestal Spread’ in e−
Vcal Thr. Width in e−
A
B
C
< 500
< 10 %
< 2500
< 200
< 1000
< 20 %
< 5000
< 400
> 1000
> 20 %
> 5000
> 400
increasing radiation damage the modules will be operated at increasing depletion voltage VOP . In
order to ensure reasonable behaviour at higher operating voltages a limit was set on the slope of
the I-V curve
I(VOP )/I(VOP − 50 V) ≤ 2.
Leakage current conversion
The grading criteria for the sensor leakage current was defined at room temperature. Therefore the
leakage current measured at −10◦C had to be recalculated to the corresponding leakage current at
room temperature, using
−∆E
I ∝ T e 2kT
As shown in Fig. 35 the mean of the ratio of recalculated and measured current at room temperature is around 1.5. Consequently the limit for the current measured at −10◦C was 1.5 times
higher than for the current measure at 17◦C.
Grading scheme
Table 11. Grading based on module leakage current
Grade
meas (150V )
I+17
o
recalc (150V )
I−10
o
A
< 2 µA
< 3 µA
B
< 10 µ A
< 15 µ A
C
> 10 µ A
> 15 µ A
6.4 Module production quality
The module production progress is shown in Fig. 36. The production was officially completed in
March 2008.
– 37 –
Figure 35. Ratio of measured current at T = 17◦C and recalculated current measured at T = −10◦C
Figure 36. Ratio of measured current at T = 17◦C and recalculated current measured at T = −10◦C
6.5 Overall production quality
6.6 Summary of mounted modules
Acknowledgments
We like to thank ...
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– 39 –