Polytech`Montpellier – MEA M2 EEA – Systèmes

Cours CIA Avancé - 2013/2014 - Séance 1
09/03/2014
Polytech’Montpellier – MEA
M2 EEA – Systèmes Microélectroniques
Advanced Analog IC Design
Chapter I
Introduction
Pascal Nouet / 2013-2014
[email protected]
http://www2.lirmm.fr/~nouet/homepage/lecture_ressources.html
Outline of the complete course (four
sessions – 3 hours each)
2
• Future of CMOS circuits: FinFET or FDSOI
• Analog IC Design Flow
• Advanced specifications
• Advanced design techniques
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Cours CIA Avancé - 2013/2014 - Séance 1
09/03/2014
1.1. History: today and future…
• Today: 22nm node
– CMOS bulk with
Na=1018 atoms/cm3
– What is the number of
dopant in a minimum
size channel?
– Cubic volume of 22nm
of side  10-17 cm3
– 10 dopants
d
t !!!
• Strong variability of
the threshold voltage
• Increase of leakage
currents
"Study of Random-Dopant-Fluctuation (RDF) Effects for the Trigate Bulk MOSFET« , IEEE Trans. on Electron Devices, 56(7):1538-1542, July 2009.
1.1. History: today and future…
• Solutions for threshold voltage variability (and Ion/Ioff)
– If substrate doping cannot be controlled then let’s work with
undoped silicon
– Solution 1: SOITEC-ST Microelectronics  planar Fully-Depleted
SOI
http://hothardware.com/News/SoiTec-Announces-New-SOI-Roadmap--Industry-Uptake-Remains-Unclear/
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Cours CIA Avancé - 2013/2014 - Séance 1
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1.1. History: today and future…
• Solutions for threshold voltage variability (and Ion/Ioff)
– If substrate doping cannot be controlled then let’s work with
undoped silicon
– Solution 2: INTEL  3D FinFETs or tri-gate transistors
(Berkeley, 1999)
http://en.wikipedia.org/wiki/Multigate_device
https://eda360insider.wordpress.com/2011/06/19/are-finfets-inevitable-at-20nm-“yes-no-maybe”-says-professor-chenming-hu/
FD-SOI Technology
6
http://www.youtube.com/watch?v=uvV7jcpQ7UY
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Cours CIA Avancé - 2013/2014 - Séance 1
FinFET Technology
09/03/2014
7
http://www.youtube.com/watch?v=Jctk0DI7YP8
Outline of the complete course (four
sessions – 3 hours each)
8
• Future of CMOS circuits: FinFET or FDSOI
• Analog IC Design Flow
• Advanced specifications
• Advanced design techniques
4
Cours CIA Avancé - 2013/2014 - Séance 1
09/03/2014
9
Analog IC Design Flow
Specifications
Choice of the
architecture
From
the
Just
designer
to be sure
point!!!of
operating
point,
gain,
bandwidth,
noise,
view:
next
THE
step
fabrication
cost
$
saturations, input
number
ofmore
stages,
slew-rate,
stability,
CMRR,
(analog
(10
layout
-100k$)
is
and
expert
time
and output ranges,
AC
small-signal
output
stage,
input
andto
output
dynamic
(few
than
weeks
digital
layout)
few months)
MC Simulations
gain, PSRR,
output
simulations
folded
cascode,
ranges,
output
resistance,
resistance differential
and
output
output,
t t current,
t ……
current, … output
Initial sizing
(1st
(1st order
order
models)
DC simulations
Verify cell specifications vs
stability, gain,
technology spreadings
bandwidth, CMRR,
Verify system-level
Application(variability)
and mismatches
PSRR, capacitive specifications
load
Temperature
and Power
Post-layout
Specific
effects,
Layout …
Supplies
simulations
Simulations
(DC, AC, TRAN)
10
Analog IC Design Flow
Specifications
Choice of the
architecture
Initial sizing
(1st order
models)
MC Simulations
AC small-signal
simulations
(gain, fc)
DC simulations
(Op. point)
ApplicationSpecific
Simulations
(DC, TRAN, AC)
Layout
Post-layout
simulations
5
Cours CIA Avancé - 2013/2014 - Séance 1
09/03/2014
Outline of the complete course (four
sessions – 3 hours each)
11
• Future of CMOS circuits: FinFET or FDSOI
• Analog IC Design Flow
• Advanced specifications
–
–
–
–
–
Offset considerations
Common Mode Rejection Ratio
Design for low mismatches
Noise fundamentals
Characterization
• Advanced design techniques
Offset considerations
12
• Definition: “input offset” of a differential
amplifier is the differential input voltage that
leads to a zero output voltage
Symmetrical power supplies !!!
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Cours CIA Avancé - 2013/2014 - Séance 1
09/03/2014
13
Offset considerations
• Impact of offset on a simple design: high for
low-input levels
iin 
vin  vos
 vout  vos  RF .iin  596mV
1k
• The gain is 60 instead of 100
14
Offset considerations
• Offset is a random phenomenon due to:
– Technology
gy spreading
p
g  low “frequency”
q
y variations
(die to die ; wafer to wafer ; run to run)
– Mismatches  high “frequency” variations
(device to device)
– Variability  hot topic covering both previous origins
• affecting technology parameters and dimensions
• generally following a Gaussian distribution.
distribution
• Propagation to circuit behavior
– Example: incertitude on saturation current
– µCox, W/L and Vt are affected
µCox W
I dsat 
2
L
V
gs
Vt 
2
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Cours CIA Avancé - 2013/2014 - Séance 1
Offset considerations
09/03/2014
15
• Gaussian distribution basics
– For a large
g number of identical devices the
distribution of actual Vt (µCox, W/L) follows a
Gaussian distribution
– 0.5% of the values are more
than ±3 away from the average
value
– 6 designs
g are then the standard
in industry
 99.5% of yield in absence of defects
– Run to run  (technology spreading) is much higher
than device to device  (mismatches)
 MC simulations
Offset considerations
16
• Standard deviations are related to design !!!
– Set of equations
q
can be
A
Vt  Vt
found in the literature
WL
– Vt spreading increases with the
AVt  tox 4 NB (mV.µm)
substrate doping and the oxide
thickness
– Vt spreading decreases with the area of the
transistor
– PMOS fabricated in a N-well exhibits more Vt
spreading (ND>>NA)
– Overall, Vt spreading reduces with modern
technologies (seems to saturate at around 3mV.µm)
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Cours CIA Avancé - 2013/2014 - Séance 1
09/03/2014
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Offset considerations
µCox
• µCox mismatches
µCox
– Similar expressions
p
than for Vt
AµCox
W / L
• W/L mismatches
t
Vt

1,2mV
 0,2%
600mV
 µC
ox
µCox
AµCox
WL
 0,0056 µm
1 1

W/L
W 2 L2
AW / L  0,02µm
• Example: 100µm/1µm NMOS
in a 0,6 µm tech.
V

 AW / L
W / L
 0,00056  0,056%
W/L
 2%
– 50% more for a PMOS
– 10 times less for MOST on the same die (mismatches)
18
Offset considerations
• Random offset in a current mirror
Iin
T1
I S  I dsat 
IS
T2
µCox W
Vgs Vt 2
2 L
Vs
• Design tips
 Large area and Veff, long
I
S
IS

2.Vt
Vgs Vt

 µC
ox

W / L
µCox W / L
• W=100µm ; L=1µm ; Veff=0,1V
0,24% 56 ppm 0,2%
• W=10µm ; L=10µm ; Veff=1V
0,024% 56 ppm 0,028%
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Cours CIA Avancé - 2013/2014 - Séance 1
09/03/2014
19
We’ve already studied…
Somedesign
variability
• Analog
flowparameters (wafer to wafer)
AV g must fit specifications
in the typical
yp
case
 µCoxp AµCox
V – A design
W / L
1 1

AWpossible
 2
– A WL
design must also fit specifications forall
/L
2
µCox
WL
/
W
L
W
L
of: process (variability in process
AV  combinations
12mV.µm
AW / L  0,and
02µm
 0,0056µm
parameters andAµC
dimensions),
temperature
power
ox
t
t
t
AVt  supply
8mV.µm 6 designs
• Advanced specifications and variability
– Uncertainties
U
t i ti ttranslate
l t iin a Idsat standard
t d dd
deviation
i ti
I
dsat
I dsat

2.Vt
Vgs Vt

 µC
ox

W / L
µCox W / L
 ...
– Random offset in a simple current mirror…
• Large transistors and large Veff
20
Offset considerations
• Random offset in a differential pair
with resistive load and symmetrical
supply voltages
vod
RL I B
vos
 g m RL 
Veff
• Spreading in load resistance
vod  RL
IB
RL Veff
 vos 
2
RL 2
• Other spreading
vod  RL .I dsat
 vos 
I dsat Veff
I dsat 2

I dsat 2.Vt µCox W / L



I dsat
Veff
µCox
W/L
 vos  Vt 
Veff  RL µCox W / L 




2  RL
µCox
W / L 
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Cours CIA Avancé - 2013/2014 - Séance 1
Offset considerations
09/03/2014
21
• But offset can be also systematic
– due to the chosen architecture, the bias p
point, a
wrong layout (systematic mismatch)…
– Must be fixed by designer !!!
• Examples
– Related to design (layout)
Veff 3  Veff 1  RS iout 2  iout 2  iin  g m RS iout 2
– Related to usage
• If Vds2>Vds1 (Vt+Veff1)
iout 1  iin  g out Vds 2  Vds1 
Laboratory work
22
• Random offset in a current mirror
I
– Using
g T1 and T2 at minimum size
I
and Iin=7µA, let’s record Is=f(Vs)
T1
T2 Vs
– Let’s identify Vs0 such that Is=Iin.
– Let’s run MC simulations (process only then mismatch
only then all) and analyze Is=f(Vs) and Is(Vs0).
– Do the same simulation for W/L multiplied by ten and
then divided by ten
– Let’s compare the  obtained for the three
simulations
– Conclusions
in
S
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Cours CIA Avancé - 2013/2014 - Séance 1
09/03/2014
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Laboratory work
• Fully differential pair
– Let’s simulate a fully
y differential pair
p
with IB=14µA and W/L=10 using ideal
resistors of 200k. One input is
fixed to 1.65V while the other one
is swept.
– Using the calculator functions compare
and cross determine input voltage that leads to
Vo1=Vo2.
– Run a MC analysis to determine typical offset
– Do the same analysis for different W/L, real
resistors and finally using the previous current
mirror. Let’s conclude.
Connexion serveur Linux MEARH14
• mearh14.pedagogie-virtuel.polytech.univ-montp2.fr
• mkdir
AMS035
mkdir = make directory
(dir name can be choosen freely)
• cd
AMS035
cd = change directory
• source
/soft_eii/Cadence/.config_AMS410
• ams_cds -64 -tech c35b4
-mode virt &
will prepare your folder (directory) to design in AMS
C35B4 technology
• Next runs : ams_cds -64
12
Cours CIA Avancé - 2013/2014 - Séance 1
09/03/2014
Outline of the complete course (four
sessions – 3 hours each)
25
• Future of CMOS circuits: FinFET or FDSOI
• Analog IC Design Flow
• Advanced specifications
–
–
–
–
–
Offset considerations
Common Mode Rejection Ratio
Design for low mismatches
Noise fundamentals
Characterization
• Advanced design techniques
Common Mode Rejection Ratio, CMRR
26
• Definition: CMRR characterizes the ability of a
differential amplifier to reject the common
mode
V  VMC 
Vd
2
+
Vd
Vs  Ad  Vd  AMC VMC
-
V  VMC 
CMRR 
Ad
AMC
Vd
2
 A
CMRRdB  Ad ,dB  AMC ,dB  20 log d
 AMC



13
Cours CIA Avancé - 2013/2014 - Séance 1
09/03/2014
Common Mode Rejection Ratio, CMRR
27
• Random CMRR in a differential
pair
Ad 
vod
vid
Amc 
 g m RL 
vinc  0
vod
vinc
RL I B
Veff
 0  CMRR  
vid  0
• Impact of spreading
spread ng in
n RL
– vinc vinc/RB in the current source output resistance
 vod  RL
vinc
v
 Amc  od
2 RB
vinc

vid  0
2 g m RB
RL
 CMRR 
2 RB
RL RL
Common Mode Rejection Ratio, CMRR
28
• Without RL spreading, vinc/(2.RB)
in each load resistance
• Impact of spreading in MOST
vod  RL I ( RL )  RL
vinc I dsat
2 RB I dsat
 2.Vt µCox  W L 




 Veff

W
L
µC
ox


g m RL
2 g m RB
 CMRR 

RL 2.Vt µCox  W L
Amc



RL
Veff
µCox
W L
 Amc 
vod
R
 L
vinc 2 RB
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Cours CIA Avancé - 2013/2014 - Séance 1
09/03/2014
29
Random CMRR and offset trade-off
• Design for low offset and high CMRR
vos  Vt 
Veff  RL µCox W L 
2 g m RB

 CMRR 


W L 
2  RL
µCox
RL 2.Vt µC ox  W L



RL
Veff
µC ox
W L
vos  CMRR  g mVeff RB  I B RB
The lower the offset, the higher the CMRR !!!
1. Optimize for low offset
– Low Veff (0,1V), large transistors, matched resistors
 reduce Vt spreading and current mismatch
2. Optimize for large CMRR  High gm(IB) & RB
30
Systematic CMRR
• CMRR can be also systematic: example with a
differential pair with referenced output
– Current source output resistance: RB
– Common Mode VMC
 change bias current VMC/RB
T3
– VMC/RB does not equally share
between T1 and T2
I
– Small-signal
Small signal analysis to calculate
V+
induced output voltage
Vdd
T4
Id4
Id2
d1
CMRR  2 g m 2 g m 3 rds 1 R B
T1
T2
Vout
V-
Ibias
15