Serial ATA - Ingenieurbüro Scholz

Serial ATA
Seminar SATA II
Thorsten Scholz
[email protected]
1
Serial ATA
Seminar SATA II
© 2008 Ingenieurbüro T. Scholz, www.IBS-Networks.de, all rights reserved
No part or whole of this document may be reproduced,
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into any language without prior permission of Ingenieurbüro Scholz.
This document is provided "as is", without warranty of any kind,
neither expressed nor implied, including but not limited to a particular
purpose. Ingenieurbüro Scholz may make improvements and/or changes in this
document without notice at any time. 2
Contents
• General Overview
• Electrical
El t i l Interface
I t f
• Data Communication
• Application Layer
• SATA Link Expansion
• SATA Integrated Circuits
3
Serial ATA
General Overview
Standards
Topology
Terms and Definitions
4
SATA Overview
Responsibilities
espo s b t es
• Serial ATA International Organization (SATA-IO)
• www.sata-io.org
• Dell, HP, Hitachi, Intel, Seagate, Western Digital, …
• Connectors: SFF, www.sffcommittee.com
• (P)ATA Standards
• InterNational Committee for Information Technology Standards, T13 Group
• www.incits.org
i it
• www.t13.org
5
SATA Overview
Parallel
a a e ATA
• ATA = Advanced Technology Attachment
• Parallel ATA (PATA)
• 40/80 Pin cable
• 16 Bit bus width
• Up
p to 66 MHz
Æ max. Data Rate of 133 MB/s
• 2 Connections per Controller (Master & Slave) in bus connection
8
SATA Overview
Serial
Se
a ATA
• Register-compatible with Parallel ATA
• Command set from PATA-6 used
• LVD
V S
Signaling
g
g
• Data rates of 1,5 Gbps and 3,0 Gbps
• Line coding for fault-tolerance and signal integrity
• Point-to-Point connections (no Master/Slave)
• 7-Pin Interface
• May
M use S
Spread
dS
Spectrum
t
Cl
Clocking
ki to
t reduce
d
EMI
9
SATA Overview
Co pat b ty
Compatibility
• SATA is Software compatible to Parallel ATA
• Identical Register Interface
OS
OS
Application
Application
Application
Driver
Parallel
ATA
M
Adapter
S
Application
Application
Driver
Serial
ATA
HBA
Application
P ll l ATA
Parallel
S i l ATA
Serial
10
SATA Overview
Serial
Se
a ATA – Link Speed
• Data rates of 1,5 Gbps and 3,0 Gbps
• 20% used for line code
• Link layer
ye speed oof 150/300
50/300 MB/s
/s
• Separate Transmit and Receive Pairs
• “Full-Duplex”-operation
• BUT: only one frame active at a given time
• Only Handshake/Error Control in backward direction
12
SATA Overview
Terms
e sa
and
d Definitions
e to s
• Gen1
Defines SATA Interface with transmission rate of 1,5
Gbps
• Gen2
Defines SATA Interface with transmission rate of 3,0
Gbps
Gb
• GenX
Defines SATA Interface with any transmission rate
13
Serial ATA
Electrical Interface
Usage Models
Cables and Connectors
Analog Frontend (AFE)
14
Electrical Interface
Usage Models
ode s
• Internal connection Host to Device
• Short Backplane to Device
• Long
o g Backplane
c p e too Device
ev ce
• Internal Cabled Disk Arrays
• System to System Interconnects
• Serial Attached SCSI (SAS)
15
Electrical Interface
Reference
e e e ce Points
o ts
• Layer Association: Physical Interface (PHY)
• Divided into two Generations: 1 (1,5 Gbps) and 2 (3 Gbps)
• Reference/Compliance
e e e ce/Co p ce Points
o s described
desc bed by Electrical
ec c Specification:
Spec c o :
• Gen1i:
Internal host to device applications
• Gen1m:
Short backplane and external single-lane
single lane cabling applications
• Gen1x:
Extended length for long backplane and external multi-lane
applications
pp
• Same association for Generation 2 specifications (Gen2i, …)
16
Electrical Interface
Internal
te a Power
o e Cab
Cable
e
Pin
Contact Description
P1
3,3 Volt
P2
3 3 Volt
3,3
V lt
P3
3,3 Volt Pre-Charge
• 5 Volt power and pre-charge
P4
GND
• 12 Volt power and pre-charge
P5
GND
P6
GND
• Ground (GND)
P7
5 Volt Pre-Charge
• Device Activity Signal (DAS) or
P8
5 Volt
P9
5 Volt
P10
GND
P11
DAS/DSS
P12
GND
P13
12 Volt Pre
Pre-Charge
Charge
P14
12 Volt
P15
12 Volt
• Cable consists of
• 3,3 Volt power and pre-charge
• Disable Staggered Spinup (DDS)
• 5 AWG 18 wires (1 mm²)
• 3 wires for voltage
• 2 wires for GND
35
Electrical Interface
Cable
Cab
e Electrical
ect ca Spec
Specification
cat o
Description
Gen1i/Gen2i
Gen1m/Gen2m
Gen1x/Gen2x
Connector Impedance
100 Ohms ±15%
100 Ohms ±15%
100 Ohms ±10%
Cable Impedance
100 Ohms ±10%
100 Ohms ±10%
100 Ohms ±5%
±5 Ohms
±5 Ohms
±5 Ohms
20 – 40 Ohms
20 – 40 Ohms
25 – 40 Ohms
Maximum Insertion Loss (10-4500 MHz)
6 dB
8 dB
16 dB
Maximum Crosstalk (Single Lane)
26 dB
26 dB
-
Maximum Crosstalk (Multilane)
30 dB
30 dB
30 dB
25 ps (20/80)
150 ps (20/80)
150 ps (20/80)
M i
Maximum
Intersymbol
I t
b l Interference
I t f
50 ps
50 ps
60 ps
Maximum Intra-Pair Skew
10 ps
20 ps
20 ps
Pair Matching
g Impedance
p
Common Mode Impedance
Maximum Rise Time
47
Electrical Interface
Voltage
o tage levels
e es
• Input and Output voltage levels dependant on usage model
Description (all values in mV)
Output Voltage
Input Voltage
Output Voltage
Input Voltage
Gen_i
Gen1
Gen2
Gen_m
500 (400-600)
400 (325-600)
400 (240-600)
400-700
275-750
Gen_x
400-1600
275-1600
400-1600
240-750
275-1600
57
Electrical Interface
Hot-Plug
ot ug
• Surprise Hot-Plug capable
• Insertion or Removal under power
• GenXx, GenXm and GenXi in Short Backplane applications
• AC coupling
• OS-Aware Hot-Plugg capable
p
• Insertion or Removal with unpowered or powered backplane
• Data connector is in defined state
• The removal of a rotating device should be prevented by the system
designer!
58
Electrical Interface
Impedance
peda ce Ca
Calibration
b at o
• Host and Device may employ on-chip impedance matching
• Host launches a step-waveform
• Impedance measurement using TDR techniques
• Adjusts impedance settings as necessary
• Device assumes calibrated far
far-end
end
• Uses this calibration as reference for its own calibration
59
Electrical Interface
Interface
te ace Power
o e States
• PHYRDY
• Phy logic and PLL are on and active
• Interface is synchronized and capable of transmitting and receiving data
• Partial
• Phy
y logic
g in reduced ppower state
• Signal lines are at common mode voltage (neutral)
• Transition latency to PHYRDY no longer than 10 µs
• Slumber
• Phy logic in reduced power state
• Transition latency to PHYRDY no longer than 10 ms
68
Electrical Interface
Elasticity
ast c ty Buffer
u e
• Serial ATA allows clock tracking as well as non-tracking
implementations
• For non-tracking implementations an Elasticity Buffer is required
• Phy layer supports unlimited frame size, Elasticity Buffer is finite
Æ Phy layer solution needed
• Maximum frequency difference is up to 0,5% for an SSC device
talking to a non-SSC
non SSC device
• Phy layer inserts two ALIGN primitives every 254 DWORDS
Æ Elasticity Buffer of 64 Bits (2 DWords) is sufficient
69
Serial ATA
Data Communication
Task Overview
Encoding/Decoding
Primitives and Frames
Data Flow
Frame Information Structure
70
Data Communication
Link Layer:
aye Tasks
as s
• Framing
• CRC Generation and Check
• Flow
ow Co
Control
o and
d Handshaking
ds
g
• Encoding and Decoding
• Scramble / Descrambling for EMI purposes
71
Data Communication
Link Layer:
aye Encoding
cod g
• Character to be transmitted consists of 8 Data Bits and Control
indicator
• Control indicator bit is D for data and K for control information
Æ Total of 8+1 Bit to be encoded to 10 Bit (8B/10B code)
• Unencoded Bits are named A to H,
H Control indicator named Z
• Each character is given a name by Zxx.y with
• Z is the value of the control indicator
• xx is the decimal value of bits A to E
• y is the decimal value of bits F to H
Bit
7
6
5
4
3
2
1
0
Ctrl
Unencoded
H
G
F
E
D
C
B
A
Z
N t ti
Notation
y
xx
Z
72
Data Communication
Link Layer:
aye Notation
otat o
• Notation of 0xBC Control
→ 0b10111100 K
→ K28.5
• Notation
N t ti off 0x4A
0 4A Data
D t
→ 0b01001010 D
→ D10.2
D10 2
• Only 2 control characters exist: K28.3 and K28.5
Æ If not stated otherwise Control
variable Z is always D
Bit
7
6
5
4
3
2
1
0
Ctrl
Unencoded
H
G
F
E
D
C
B
A
Z
N t ti
Notation
y
xx
Z
73
Data Communication
Link Layer:
aye Encoding
cod g Sc
Scheme
e e
• Widmer and Franaszek 8B/10B Code
• Two-stage coding: 5B/6B and 3B/4B
• 55B/6B
/6 hass 5 bits
b s input
pu pplus
us running
u
g ddisparity
sp y
• 3B/4B has 3 bits input plus running disparity
• Running disparity is
• Negative
if output bits contain more zeroes than ones
if output bits
bi are 111000 or 1100
• Positive
if output bits contain more ones than zeroes
if output bits are 000111 or 0011
• Same
if output bits have equal number of ones and zeroes
74
Data Communication
Link Layer:
aye Encoding
cod g Sc
Scheme
e e
• Code guarantees to generate always opposite disparity or neutral
• Aim of Code
• DC free output
• Clock containment of output
• Output notation in small letters
• EDCBA
encoded to abcdei
• HGF
encoded
d d tto fghj
f hj
• Final coded word is abcdeifghj
• “a” is transmitted first
75
Data Communication
Link Layer:
aye Code Table
ab e 5
5B/6B
/6
• rd’ indicates whether incoming disparity is changed (-rd) or not (rd)
76
Data Communication
Link Layer:
aye Code Table
ab e 3
3B/4B
/
• rd’ indicates whether incoming disparity is changed (-rd) or not (rd)
• Special case for input Dxx.7: Coding depends on previous 2 bits
77
Data Communication
Link Layer:
aye Code Table
ab e Control
Co t o Codes
• Existence of 2 Control characters K28.3 and K28.5
• Any control characters inverts the running disparity
• rd’ is always -rd
78
Data Communication
Link Layer:
aye Encoding
cod g
• Encoding of Data Byte: 0x9A, last rd should be negative (rd-)
• Binary representation 0x9A __ __ __ __ __ __ __ __
•C
Character
c e notation
o o
D___.__
.
• Binary 5B/6B output
__ __ __ __ __ __, rd __
• Binary 3B/4B output
__ __ __ __, rd __
• Resulting 8B/10B output
__ __ __ __ __ __ __ __ __ __, rd __
79
Data Communication
Link Layer:
aye Encoding/LUT
cod g/ U
• Encoding Examples
• Incoming rd-, 0x4A D10.2
→ 010101 0101 rd- (neutral encoding)
• Incoming rd+, 0xEB D11.7
→ 110100 1000 rd- (P7 replacement)
• Incoming rd-, 0x00 D0.0
→ 100111 0100 rd-
• Incoming rd+, 0xF8 D24.7
→ 001100 1110 rd+
• Three previous tables may be combined to one lookup table
• 256 plus 2 entries
80
Data Communication
Primitive
t e Format
o at
• All Primitives begin with a Control character K28.3 or K28.5
• Followed by 3 non-control characters to complete DWord
• 88B/10B
/ 0 Encoding
cod g applies
pp es
• ALIGNP (D27.3 D10.2 D10.2 K28.5) is special primitive
• Command:
C
d Phy
Ph llayer re-adjusts
dj
internal
i
l operations
i
• Only primitive that uses the K28.5 Control character
• Has neutral disparity, can be injected without changing rd
• May be consumed by Phy layer or dropped by Link layer
85
Data Communication
Primitives:
t es Frame
a e Example
a pe
• Frame transmission
from host to device
Host
Device
Description
X RDY
X_RDY
R RDY
R_RDY
Device decodes X
X_RDY
RDY and answers R
R_RDY
RDY
X_RDY
R_RDY
SOF
R_RDY
Data
R_RDY
Data
R_IP
Data
R_IP
EOF
R_IP
WTRM
R_IP
WTRM
R_IP
Device has received EOF and computes CRC
WTRM
R_OK
CRC OK device sends R_OK
WTRM
R_OK
SYNC
R OK
R_OK
SYNC
R_OK
Host has decoded R_RDY and starts frame
Device has decoded SOF and sends R_IP
Host has decoded R_OK
R OK and sends Idle
94
Data Communication
Primitives:
t es Flow
o Co
Control
t o Example
a pe
• Frame transmission
from host to device
Host
Device
Description
SOF
R RDY
R_RDY
Host has decoded R_RDY
R RDY and starts frame
Data
R_RDY
Data
R_IP
Data
R_IP
HOLD
R_IP
HOLD
R_IP
HOLD
HOLDA
Device has decoded HOLD and sends HOLDA
Data
HOLDA
Host resumes data transfer
Data
HOLDA
EOF
R_IP
WTRM
R_IP
Device has received EOF and computes CRC
WTRM
R OK
R_OK
CRC OK device sends R
R_OK
OK
WTRM
R_OK
Device has decoded SOF and sends R_IP
Host send buffer empty sending HOLD
95
Data Communication
Primitives:
t es Co
Continue
t ue Example
a pe
• Frame transmission
from host to device
Host
Device
Description
X RDY
X_RDY
R RDY
R_RDY
Device decodes X
X_RDY
RDY and answers R
R_RDY
RDY
X_RDY
R_RDY
SOF
CONT
Data
any
Data
R_IP
Data
R_IP
EOF
CONT
WTRM
any
WTRM
any
Device has received EOF and computes CRC
CONT
R_OK
CRC OK device sends R_OK
any
R_OK
SYNC
CONT
SYNC
any
Host has decoded R_RDY and starts frame
Device has decoded SOF and sends R_IP
Host has decoded R_OK
R OK and sends Idle
96
Data Communication
Primitives:
t es Co
Connection
ect o Initt
• Initialization of
Communication
• Not temp. correct
• Temporally
T
ll correctt
Host
Device
Description
COMRESET
Idle
Host issues COMRESET (informative)
Idle
COMINIT
Device issues COMINIT (informative)
COMWAKE
Idle
Host issues COMWAKE (informative)
Idle
COMWAKE
Device issues COMWAKE (informative)
D10.2
ALIGN
Host tries to lock on devices ALIGN
ALIGN
ALIGN
Host locked on ALIGN sends ALIGN now
ALIGN
SYNC
Device locked on Host-ALIGN, sending SYNC
ALIGN
SYNC
ALIGN
SYNC
ALIGN
SYNC
ALIGN
SYNC
Host detected 3rd SYNC from Device
X RDY
X_RDY
SYNC
Host wants to transmit data
X_RDY
SYNC
Host detected 1st SYNC from Device
93
Data Communication
Primitives:
t es Co
Collision
so
• Frame transmission
from host to device
Host
Device
Description
SYNC
SYNC
Idle
X_RDY
SYNC
Host signals transmission
X_RDY
X_RDY
Device signals transmission
X_RDY
X_RDY
Device detects hosts transmission
R_RDY
X_RDY
Host detects device transmission
R_RDY
X_RDY
R_RDY
SOF
R_RDY
Data
R_IP
Data
R_IP
EOF
R_IP
WTRM
R IP
R_IP
WTRM
R_OK
WTRM
Device detected R_RDY, sends data
97
Data Communication
ATA Registers
eg ste s a
and
dS
Signals
g as
• Serial ATA is compatible with ATA Software
• ATA “emulation” needed
• Host
os “thinks”
s oof w
writing
g to
o ATA registers
eg s e s
• No direct access possible in SATA
Æ SATA holds copy of devices register block
Æ Named “Shadow Register Block”
• Writing
W iti to
t this
thi block
bl k triggers
ti
Register
R i t Transfer
T
f to
t Device
D i
• Signal INTRQ is reflected by a bit in a register
113
Data Communication
ATA Signals
Sg as
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Signal Name
/RESET
GND
DD7
DD8
DD6
DD9
DD5
DD10
DD4
DD11
DD3
DD12
DD2
DD13
DD1
DD14
DD0
DD15
GND
KEY
Description
Reset
Ground
Data 7
Data 8
Data 6
Data 9
Data 5
Data 10
Data 4
Data 11
D t 3
Data
Data 12
Data 2
Data 13
Data 1
Data 14
Data 0
Data 15
Ground
Key (Pin missing)
Pin
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Signal Name
DMARQ
GND
/DIOW
GND
/DIOR
GND
IORDY
SPSYNC:CSE
L
/DMACK
GND
INTRQ
/IOCS16
DA1
PDIAG
DA0
DA2
/IDE_CS0
/IDE_CS1
/ACTIVE
GND
Description
DMA Request
Ground
Write Strobe
Ground
Read Strobe
Ground
I/O Ready (obsolete)
Spindle Sync or Cable
Select
DMA Acknowledge
G
Ground
d
Interrupt Request
IO Chip Select 16
Address 1
80-pin
80
pin cable detect
detect.
Address 0
Address 2
Chip Select
Chip Select
Led driver
Ground
114
Data Communication
FIS: Register
g
Host → Device
• Transfers contents of Shadow Register Block to device
• FIS Type 0x27, Length of 5 DWords (20 Bytes)
• PM Port
Device port address (e.g. Port Multiplier)
•C
Command, set if command register addressed, not set if control r.
115
Data Communication
FIS: Register
g
Host → Device
• Command, Features, LBA Low/Mid/High, Device, Control and Sector Count
correspond to the appropriate registers in the Shadow Register Block
• LBA Low/Mid/High (exp), Features (exp) and Sector Count (exp) correspond
to the appropriate expanded fields in the Shadow Register Block
• All reserved field should be cleared on write and ignored on read
116
Data Communication
FIS: Register
g
Device → Host
• FIS Type of 0x34
• Used by device to indicate command completion
• I is Interrupt Bit and reflects the interrupt line of the device
• Status and Error contain the appropriate values of the Shadow Register Block
117
Data Communication
FIS:
S Data
ata ((Bidirectional)
d ect o a )
• Transportation of payload data
• Data read or written to number of sectors, no register transfers
• Ge
Generated
e ed by Host
os or
o Device
ev ce
• Generally one element of sequence of transactions leading to data
transfer
• In DMA operation multiple Data FIS may follow
• With PIO mode number of bytes transferred shall be equal to
bytes indicated in Transfer Count field
• Recipient is not expected to buffer data for CRC checking
126
Data Communication
FIS:
S O
Overview
e e
• FIS
H->D D->H
Type
• Register
X
X
0x27 / 0x34
X
00xA1
X
0x41
• DMA Activate
X
0x39
• PIO Setup
X
0x5F
• Se
Set Device
ev ce Bitss
• DMA Setup
X
• Data
X
X
0x46
• BIST A
Activate
ti t
X
X
0 58
0x58
127
Data Communication
Protocol:
otoco Device
e ce Power-On
o e O
• Hardware reset detected by Phy (Power-on or COMRESET)
• State: Device Hardware Reset (DHR)
• After
e COMRESET
CO
S iss negated
eg ed hardware
dw e iss initialized
ed and
d powe
power-on
o
self-test is executed
• POST successful: Device sends Register
g
FIS with
Sector Count = 1, LBA = 1, Device = 0, Error = 1, Status 0x00 - 0x70
• POST failure: Device sends Register FIS with
Sector Count = 1, LBA = 1, Device = 0, Error = any but 1, Status 0x00 - 0x70
• Device transitions to Device Idle (DI) state
128
Data Communication
Protocol:
otoco Device
e ce Software
So t a e Reset
eset
• State: Device Software Reset (DSR)
• Software reset by Register FIS (SRST-Bit set in control register)
ÆC
C-Bit must
us be set
se too zero
e o too address
add ess control
co o register
eg s e
• Software reset by Register FIS (SRST-Bit cleared)
• Device initializes and executed diagnostics (same as DHR)
• Result is transferred to Host via Register FIS
• Transition to Device Idle (DI)
129
Data Communication
Example:
a p e Software
So t a e Reset
eset
H t
Host
Transmit C=0, SRST=1
Transmit C=0, SRST=0
D i
Device
Register
g
FIS
Register FIS
Process command
Process command
Initialization
and Self-Test
Update Shadow
Register Block
Register
g
FIS
130
Data Communication
Protocol:
otoco Device
e ce Idle
de
• Device waits for FIS, state is Device Idle (DI)
• While idle device or Host send SYNC primitives
• FIS
S reception:
ecep o :
• Register FIS, C-Bit cleared, SRST set
→ DSR (Reset)
• Register FIS
FIS, C-Bit
C Bit cleared,
cleared SRST cleared
→ DI (Idle)
• Register FIS, C-Bit set
→ DI2 (CheckCmd)
• DMA Setup
S t FIS
→ DI (Idle)
(Idl )
• Unexpected FIS
→ DI (Idle)
131
Data Communication
Protocol:
otoco Device
e ce Idle
de C
Check
ec Co
Command
a d
• Device received Register FIS
• State is Device Idle 2:Check_command (DI2:Check_command)
• Determine
ee
e required
equ ed command
co
d protocol
p o oco
• Non-data command
→ DND0: Non-data
• PIO data-in
data in
→ DPIOI0: PIO_in
PIO in
• PIO data-out
→ DPIOO0: PIO_out
• READ DMA
→ DDMAI0:
DDMAI0 DMA_in
DMA i
• WRITE DMA
→ DDMAO0: DMA_out
• DEVICE RESET
→ DDR0: Device_reset
132
Data Communication
Protocol:
otoco PIO
O In
0. Successfully parsed PIO In command
1. Prepare a data block for transfer
2.. Transmit
s
PIO
O Setup
Se up FIS
S too Host
os
3. Transmit Data FIS
•
If more data
d than
h 8192 B
Bytes (2048 DW
DWords)
d ) requested
d proceed
d to 11.
4. Transition to Device Idle (DI)
133
Data Communication
Example:
a p e PIO
O Read
ead from
o Device
e ce
Host
Device
Initialization of Shadow
Control Registers
Transfer Shadow
Control Registers
Update Status Register
Process command
PIO Setup FIS
Data FIS
…
Update Status Register
with E_Status
R i
Register
FIS
Update Status Register
PIO Setup FIS
Update Status Register
with E_Status
Data FIS
• Real
R l final
fi l status
t t is
i nott transferred
t
f
d
134
Data Communication
ATAPI PIO
O In
1. Host sends PACKET command via Register FIS
2. After device is ready to receive ATAPI command packet PIO
Setup FIS is transmitted to Host
3. Host writes command to Shadow Data Register and sends Data
FIS containing the command to device
4. Device processes command packet and starts delivering data
•
Data transfer announced with PIO Setup FIS to Host
•
(Multiple) Data FIS follow
5 Device
5.
D i transmits
t
it Register
R i t FIS att endd off transfer
t
f
149
Data Communication
Example:
a p e ATAPI PIO
O Read
ead from
o Device
e ce
Host
PACKET command
Device
Register FIS
Request command packet
PIO Setup FIS
Send command packet
D t FIS
Data
PIO Setup FIS
Receive data
Update Shadow Registers
Data FIS
Register FIS
Process command
Send data announcement
Send data
Send register update
150
Data Communication
PIO
O vs.
s DMA Transfers
a ses
• DMA
• Data from/for Data FIS is handled by Host DMA controller
• PIO
• Data is written to (serial) FIFO that is attached to Shadow Data Register
• Host reads Shadow Data Register
g
to get/set
g
data
• A FIFO overflow or underflow is prevented by SATA Flow Control
• Host register access time defined by PIO mode setting
151
Serial ATA
Application Layer
Host Adapter Register Interface
Parallel ATA Emulation
Native Command Queuing
HDD Activity Indication
152
Application Layer
Feature:
eatu e Native
at e Co
Command
a d Queuing
Queu g
• Allows commands to be accepted even if one or more previously
accepted commands are not completed
• All commands send must carry a NCQ tag
• NCQ tag is identifier for command “slot” in queue
• Queue size is defined in IDENTIFY DEVICE Word 75
• Status of queue is returned to Host in Set Device Bits FIS
• Set Device Bits FIS is send to Host after each successful command
completion
• Unsuccessful
U
f l command
d completion
l i is
i indicated
i di
d by
b Register
R i
FIS or
Set Device Bits FIS (both with ERR-Bit set) to Host
180
Application Layer
Feature:
eatu e NCQ
CQ Commands
Co
a ds
• NCQ consists of two commands to read and write data
Æ First-party DMA (FPDMA)
• READ FPDMA QU
QUEUED
U
00x60
60 / W
WRITE FPDMA QU
QUEUED
U
00x61
6
• FUA:
Forced Unit Access (Data must be on media)
• Prio:
Command Priority: 0 = Normal,
Normal 1 = High
Register
Features
Sector Count
LBA Low
LBA Mid
LBA High
D i
Device
Command
15 14 13 12 11 10
Prio
Reserved
9 8 7 6 5 4 3 2 1 0
Sector Count
NCQ Tag
na
LBA
LBA
LBA
FUA 1 R/0 0
R
Reserved
d
60h/61h
181
Application Layer
Feature:
eatu e NCQ
CQ Command
Co
a d Sending
Se d g
• NCQ Commands are transferred via Register FIS to device
• BSY Bit and DRQ Bit is not set
• Register
eg s e FIS
S iss used to
o inform
o Host
os oof co
command
d acceptance
ccep ce
• NCQ and “normal” commands are not allowed to mix
• If this is tried all unexecuted commands in queue are marked failed
• Host implements 32 Bit SActive Register and sets the appropriate
Bit position to 1 if a NCQ command is send with this tag
• Host mayy issue as many
y commands as there are empty
p y “slots” in
SActive
182
Application Layer
Feature:
eatu e NCQ
CQ Data
ata Delivery
e ey
• Device issues DMA Setup FIS when data is ready to be transferred
• Originating commands tag is used as buffer identifier
• Host
os controller
co o e must
us findd appropriate
pp op e context
co e for
o thiss identifier
de
e
183
Application Layer
Feature:
eatu e NCQ
CQ Data
ata Delivery
e ey
• Only one DMA Setup FIS will be send
• If transfer spans multiple Data FIS additional DMA Setup FIS not needed
• For Host to device transfers the DMA Activate FIS may be omitted
if Auto-Activate feature is used in DMA Setup FIS
• Transferringg of data depends
p
on two feature settings
g
• Non-zero buffer offsets in DMA Setup FIS
• Guaranteed in
in-order
order data delivery
• If non-zero buffer offsets are not supported or not enabled a
command is not allowed to be splitted
→ Data transfer must be satisfied to completion after Setup FIS
184
Application Layer
Feature:
eatu e NCQ
CQ Data
ata Delivery
e ey
• Non-zero buffer offsets enabled / in-order delivery enabled
• Data transfer may be interrupted after a specific DMA Setup FIS
• Interleaving of commands is not allowed
• Data transfer may be continued with additional DMA Setup FIS
• Non-zero buffer offsets enabled / in-order deliveryy disabled
• Data transfer may be interrupted after a specific DMA Setup FIS
• Interleaving of commands is allowed
• Data transfer may be continued with additional DMA Setup FIS
185
Application Layer
Feature:
eatu e NCQ
CQ Success Notification
ot cat o
• After last Data FIS of a command device sends Set Device Bits FIS
• Set Device Bits FIS includes SActive Register in Reserved field
• Bits set in the SActive fields indicate successful completion of command
• All bit position set shall be cleared in Hosts SActive Register as completed
• Host
mayy send command with Tags
g havingg value of zero in SActive
186
Application Layer
Feature:
eatu e NCQ
CQ Error
o Notification
ot cat o
• Command raises error condition on reception/processing
• Device sends Register FIS with ERR-Bit set
• Command executed in queue raises error
• Device sends Set Device Bits FIS with ERR-Bit set
• Bit for failed command ((and completed
p
commands if any)
y) also set
• Stops all command processing until Host action
• Further
h commands
d to the
h device
d i are aborted
b
d with
i h ERR-Bit
i set
• Host shall issue a READ LOG EXT command to determine exact
error condition
187
Application Layer
Example:
a p e NCQ
CQ FPDMA Read
ead
Host
READ FPDMA QUEUED
Device
Non-zero buffer offsets
In-order
Register FIS
Queuing of command
Register FIS
Additional commands
with different tags
Prepare for reception
DMA Setup FIS
Offset
O
se = 0
Data FIS
Data ready, execution of
command
Data FIS
Data FIS
…
Data FIS
Update SActive
Set Device Bits FIS
Command finished update
SActive
191
Application Layer
Example:
a p e NCQ
CQ FPDMA Read
ead
Host
READ FPDMA QUEUED
Device
Non-zero buffer offsets
In-order
Register FIS
Queuing of command
Register FIS
Additional commands with different tags
Prepare for reception
DMA Setup FIS
Offset = 0
Data FIS
Data FIS
Data ready, execution of
command
Data not ready
Additional commands to Device
Prepare for reception
DMA Setup
S t FIS
Offset = 16384
Data FIS
Data FIS
Update SActive
Set Device Bits FIS
Data ready, further
execution of command
Command finished update
SActive
192
Application Layer
Example:
a p e NCQ
CQ FPDMA Read
ead
Host
2 FPDMA READ
Both > 8192 Bytes
Device
Non-zero buffer offsets
In-order
CMD 1
CMD 2
Queuing of commands
DMA Setup FIS
Offset = 8192
Data FIS
Cmd 2 Bytes 8192 to X
DMA Setup FIS
Offset = 0
Data FIS
DMA Setup FIS
Offset = 0
Data FIS
DMA Setup FIS
Offset = 8192
Data FIS
Cmd 1 Bytes 0 to 8191
Cmd 2 Bytes 0 to 8191
Cmd 1 Bytes 8192 to X
193
Application Layer
HDD Activity
ct ty Indication
d cat o
• May be vendor-specific or Parallel ATA emulated by Host
• Emulation:
• If BSY or SActive set then
LED = On
• Else
LED = Off
• LED is valid for both Master-only
y and Master-Slave SATA Hosts
• If Master-Slave mode LED should be always on
• ATAPI devices shall not generate LED indication
• Multiple SATA channels LED indications should be connected by
wired-OR
201
Application Layer
HDD Activity
ct ty Indication
d cat o
• Activity signal shall be
• Active low
• Open collector/drain
• SATA controllers may include activity aggregated indication pin
and/or pin for each channel
202
Serial ATA
SATA Link Expansion
Port Multiplier
Port Selector
203
Serial ATA
SATA Integrated Circuits
Port Multiplier
PATA Bridge
Host controller
232
SATA Integrated Circuits
Port
o t Multiplier
utp e S
SiI 3
3726
6
• Silicon Image 3726 Port Multiplier
• 1:5 SATA II Port Multiplier
• Programmable
og
b e Tx Voltage
Vo ge
• 8 kByte FIFO buffer per device
• 32 GPIO Pins controlled by SATA (GSCR[130]-Register)
• Power Mode request support
• Integrated SATA to I2C Bridge
Picture Source: SiI 3726 Prodct Brief, SiI 3726CB364, © 2004 Silicon Image, Inc.
233
SATA Integrated Circuits
SiI 3
S
3726
6 Block
oc Diagram
ag a
Picture Source: SiI 3726 Prodct Brief, SiI 3726CB364, © 2004 Silicon Image, Inc.
234
SATA Integrated Circuits
PATA-SATA
S
Bridge
dge SiI
S 3811
38
• Silicon Image 3811 Parallel ATA to SATA Bridge
• Supports SSC Receive
• Power
owe Management
ge e
• Ultra/ATA 133 Parallel Interface
• Serial ATA 1,5 Gbps Interface
• 48 Bit LBA addressing (16 Bit Registers)
• Application: Mainboard or Device
Picture Source: SiI 3811 Prodct Brief, SiI PB-58 rev1 8/06, © 2004 Silicon Image, Inc.
235
SATA Integrated Circuits
SiI 38
S
3811 Block
oc Diagram
ag a
Picture Source: SiI 3811 Prodct Brief, SiI PB-58 rev1 8/06, © 2004 Silicon Image, Inc.
236
Serial ATA
Thanks for your Attention
240