Option Introduction à la modélisation et à la vérification des

Université Grenoble Alpes
Master 1 Informatique / MOSIG
Année 2016/2017
Option
Introduction to modeling and verification of digital systems
Exercises n°2
Exercise 1.
Give the VHDL description (entity + architecture in the dataflow style), of the circuit below
(which is a 3-bit converter binary code -> Gray code2), ignore gate delays.
X
A
B
Y
C
Z
Propose a testbench entity that enables to perform a simulation with all the possible
combinations of input stimuli.
Exercise 2.
The picture below represents a comparator for natural numbers: this circuit takes as input two nbit vectors A and B, and a carry in X_IN; it gives as output (when X_IN is '0') a bit X that equals
'1' if the natural number encoded by A is strictly greater than the natural number encoded by B,
otherwise '0'.
A0
B0
X_IN
A1
B1
A n-1 B
n-1
X n-1
X1
X2
X
We can see that this circuit is built as the repetition of a primitive component. This primitive
component takes as input one bit of the vector A, one bit of the vector B, and a carry-in, and it
2
See for example https://en.wikipedia.org/wiki/Gray_code (we will also study it later)
produces a carry-out which is propagated to the next component.
Write, in the dataflow style, the VHDL architecture of the primitive component (ignore gate
delays), which is associated with the following entity:
entity comparator_cell is
port(a, b, xe : in std_logic; x : out std_logic);
end comparator_cell;
Then give the entity Comparator of the comparator for two n-bit bit-vectors A and B (n is a
generic parameter), and its associated structural style architecture that uses the component
comparator_cell. Give also its external configuration.