Chapter 13 Embedded ARM Applications Introduction

Chapter 13 Embedded ARM
Applications
Introduction
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The VLSI Ruby II advanced communication
processor
The VLSI ISDN subscriber Processor
The OneCTM VWS22100 GSM chip
The Ericsson—VLSI bluetooth baseband
controller
The ARM7500 and ARM7500FE
The ARM7100
The SA-1100
Introduction
¾
„
„
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„
„
„
The VLSI Ruby II advanced communication
processor
The VLSI ISDN subscriber Processor
The OneCTM VWS22100 GSM chip
The Ericsson—VLSI bluetooth baseband
controller
The ARM7500 and ARM7500FE
The ARM7100
The SA-1100
The VLSI Ruby II advanced
communication processor(1)
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VLSI Technology, Inc.
For used in portable communications devices
The chip is based around an ARM core
2 Kbytes of fast on-chip SRAM
Peripheral modules:
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PCMCIA interface
Four byte-wide parallel interface
Two UARTs
The VLSI Ruby II advanced
communication processor(2)
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Synchronous communications controller module
supports a range of standard serial communication
protocols
Serial controller module provides a softwarecontrolled data port such as the I2C bus.
The external bus interface supports devices with 8-,
16- and 32-bit data buses and has flexible wait state
generation
The counter-timer block has three 8-bit counters
connected to a 24-bit prescaler
An interrupter controller gives programmable control
of all on- and off-chip interrupt sources
Support power-management mode
Ruby II advanced communication
controller organization
external
interrupts (3)
clock
clock
control
ARM
core
512 x 32
SRAM
in terrupt
controller
control
pa rallel
i/f 1,2,3,4
I/O
mode
select
PCMCIA
host
interface
co unter/
timers
external
bus
control
ho st
FIFOs
(16 x 8)
address (22)
data (8/16/32)
UAR T1
UAR T2
serial
hi gh-speed
serial i/f
serial
FIFOs
(16 x 8)
se rial
controller
pa rallel
interface 0
I 2 C, ...
8 data bits
& control
Introduction
„
¾
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The VLSI Ruby II advanced communication
processor
The VLSI ISDN subscriber Processor
The OneCTM VWS22100 GSM chip
The Ericsson—VLSI bluetooth baseband
controller
The ARM7500 and ARM7500FE
The ARM7100
The SA-1100
The VLSI ISDN Subscriber
Processor (VIP)
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VIP is a programmable engine for ISDN
(Integrated Services Digital Network; a
digital telephony standard) subscriber
communications
A full-feature ISDN terminal, supporting
voice, data and video services down the
same digital line
VIP organization
clock
clock
control
ARM6
core
ports
external
interrupts (3)
768 x 32
SRAM
interrupt
controller
control
parallel
interface
external
bus
control
G.711
codec
handset/
hands-free
B and D
channels
S0-interface
battery, volume
DRAM
controller
ADCs (2)
serial
timer &
watchdog
DSP
serial i/f
address
decoder
address (23)
data (8/16/32)
mux address
ras, cas
chip selects
Typical VIP System Configuration
volume
V24 interface
hands-free
Driver
hook switch
S0-ISDN interface
power
ROM
RAM
ISDN
Subscriber
Processor
K E Y
P A D
Introduction
„
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¾
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The VLSI Ruby II advanced communication
processor
The VLSI ISDN subscriber Processor
The OneCTM VWS22100 GSM chip
The Ericsson—VLSI bluetooth baseband
controller
The ARM7500 and ARM7500FE
The ARM7100
The SA-1100
OneCTM VWS22100 GSM Chip
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Developed by VLSI technology, Inc.
System-on-Chip design for a GSM
mobile telephone handset
Incorporating an ARM7TDMI core
(6)
JTAG
test/debug
ARM7TDMI
core
boot
ROM
interrupt
controller
UART1
radio i/f
DSP radio
port
program
ROM
Oak DSP
core
program
RAM
interrupt
controller
config./
status
high-speed
serial i/f (2)
(5)
power
manager
(4)
32 KHz
cntrl (6)
external
bus
control
DSP
subsystem
data
RAM
(4)
RTC
memory
controller
data
ROM
UART2/
IrDA
SIM i/f
ARM bus
OneCTM
VWS22100
GSM Chip
Organization
PCM i/f
DSP bus
(20)
audio i/f
hardware
coprocs
(13)
(6)
ADC
addr (20)
data (16)
(7)
keypad
scanner
(10)
GPIO
PWM
(11)
DSP Subsystem
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Based around the 16-bit Oak DSP core
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Voice coding
Equalization
Channel coding
Echo cancellation
Noise suppression
Voice recognition
Data compression
ARM7TDMI Subsystem
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User interface software
GSM protocol stack
Power management
Driving the peripheral interfaces
Running some data applications
Power Management
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Global and selective power-down modes
Ability to slow down the system clock in idle
mode
Analogue circuits also can operate at reduced
power
0n-chip analogue-to-digital converters (ADCs)
provide for the monitoring of the temperature
and battery voltage to give optimum
operation
Typical GSM Handset Architecture
SIM
card
eeprom
IrDA
speaker
mic
VWS22100
radio
module
ringer
ROM
RAM
K E Y
P A D
LCD
Introduction
„
„
„
¾
„
„
„
The VLSI Ruby II advanced communication
processor
The VLSI ISDN subscriber Processor
The OneCTM VWS22100 GSM chip
The Ericsson—VLSI bluetooth baseband
controller
The ARM7500 and ARM7500FE
The ARM7100
The SA-1100
The Ericsson-VLSI Bluetooth
Baseband Controller
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Bluetooth
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De-facto standard for wireless data
communication for the 2.4GHz band
Developed by a consortium of companies including
Ericsson, IBM, Intel, Nokia and Toshiba
Support short-range communication (from 10 cm
to 10 m)
Gross data rate of 1 Mbit/s
Piconets: frequency-hopping scheme
Bluetooth Controller Organization
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Based around a synthesized ARM7TDMI core
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Peripheral modules
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64 Kbytes of fast on-chip SRAM
A 4K byte instruction cache
Three UARTs
A USB interface
An I2C-bus interface
External bus interface
Counter/timers
Interrupt controller
EBC: Ericsson Bluetooth Core: Link Controller
functionality within the bluetooth specification
Ericsson-VLSI Bluetooth
Baseband Controller organization
clock
clock
control
ARM7TDMI
core
4 Kbyte
I-cache
internal
ROM
16K x 32
SRAM
JTAG
signals (5)
control
interrupt
controller
counter/
timers
external
bus
control
address (20)
data (8/16)
UART1,2,3
I/O
mode
select
I2 C i/f
FIFOs
EBC
block
radio interface
USB i/f
Typical Bluetooth application
flash
memory
flash
memory
address
data
Bluetooth
Baseband
Controller
control
host interface
(RS232/USB)
radio
module
Bluetooth characteristics
Process
Metal layers
Vdd
0.25 um
3
2.5 V
Transistors
Die area
Clock
4,300,000
2
20 mm
0 – 13 MHz
MIPS
Power
MIPS/W
12
75 mW
160
Introduction
„
„
„
„
¾
„
„
The VLSI Ruby II advanced communication
processor
The VLSI ISDN subscriber Processor
The OneCTM VWS22100 GSM chip
The Ericsson—VLSI bluetooth baseband
controller
The ARM7500 and ARM7500FE
The ARM7100
The SA-1100
The ARM7500 and ARM7500FE
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ARM7500 is a highly integrated singlechip computer which combines the
major components of the Acorn Risc PC
onto a single chip.
ARM7500FE adds the FPA10 floatingpoint coprocessor as an on-chip
macrocell
The Principal macrocells
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ARM CPU core: ARM710
FPA10 floating-point coprocessor (on
the ARM7500FE only)
Video and sound macrocell
Memory and I/O controller
ARM7500
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
ras[3:0]
ROM
D[31:0]
analogue
inputs
ROM
Typical
ARM7500
System
Organization
RA[11:0]
analogue
sound
video
DRAM
DRAM
cas[3:0]
LA[28:0]
interrupts
module
selects
keyboard
& mouse
I/O
module
I/O
module
BD[15:0]
ARM7500 characteristics
Pro c e s s
Me t al l ay e rs
Vdd
0.6 um
2
5V
Tran s i s t o rs
Di e are a
Cl o c k
550,000
2
70 mm
0 to 33 MHz
MIPS
Po we r
MIPS / W
30
690 mW
43
Introduction
„
„
„
„
„
¾
„
The VLSI Ruby II advanced communication
processor
The VLSI ISDN subscriber Processor
The OneCTM VWS22100 GSM chip
The Ericsson—VLSI bluetooth baseband
controller
The ARM7500 and ARM7500FE
The ARM7100
The SA-1100
ARM710a
MMU
ARM7
core
8 Kbyte
cache
LCD
controller
interrupt
controller
AMBA
ARM7100
Organization
3.6864 MHz
control
clock PLL
power
mgt.
counter/
timers
32.786 KHz
external
bus
control
RTC
osc.
UART
data (32)
DRA(13)
FIFOs
codec i/f
address (28)
DRAM
controller
RAS, CAS(8)
WE , OE(2)
sync serial
expansion
parallel I/O
PSU control
DRAM
ROM
Flash
PSU
ARM7100
The Psion
Series 5
Hardware
Organization
ADC
PC cards
infrared
IrDA Tx/Rx
digitizing
tablet
RS232
640 x 240
LCD
audio
codec
keyboard
ARM7100 characteristics
Process
Metal layers
Vdd
0.6 um
2
3.3 V
Transistors
Die area
Clock
N/A
2
N/A mm
18.432 MHz
MIPS
Power
MIPS/W
30
14 mW
212
Introduction
„
„
„
„
„
„
¾
The VLSI Ruby II advanced communication
processor
The VLSI ISDN subscriber Processor
The OneCTM VWS22100 GSM chip
The Ericsson—VLSI bluetooth baseband
controller
The ARM7500 and ARM7500FE
The ARM7100
The SA-1100
The SA-1100
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A high-performance integrated systemon-chip based around a modified
version of the SA-110 StrongARM CPU
core
Use in mobile phone handsets, modems,
and other hand held applications
Minimal power consumption
Support for Window CE environment
SA-1100
Organization
SA-1
core
mini-cache
instruction
cache
data
cache
instruction
MMU
write buffer
CPU core
data
MMU
read buffer
system bus
data (32)
LCD (5)
3.6864 MHz
32.786 KHz
I/O pins (28)
battery (3)
LCD
control
DMA
control
bridge
memory &
PCMCIA
clock
PLL
interrupt
control
serial 0
RTC
osc.
RTC
serial 1
generalpurpose I/O
control
USB (2)
SDLC (2)
IrDA (2)
serial 2
OS
timer
serial 3
power
manager
reset (2)
address (26)
reset
control
serial 4
UART (2)
Codec (4)
peripheral bus
SA-1100 characteristics
Process
Metal layers
Vdd
0.35 um
3
1.5/2 V
Transistors
Die area
Clock
2,500,000
2
75 mm
190/220 MHz
MIPS
Power
MIPS/W
220/250
330/550 mW
665/450