STA328 evaluation board
Transcription
STA328 evaluation board
AN2032 APPLICATION NOTE STA328 EVALUATION BOARD 1 DESCRIPTION The STA328 is a single chip solution for digital audio processing and control in stereo applications. It provides high-quality, high-efficiency, all digital amplification. The internal 24-bit DSP (Digital Signal Processing) allows for high resolution processing at all standard input sample frequencies. Processing includes volume control, filtering, bass management, and gain compression/limiting. Filtering includes ten user-programmable 28-bit biquads for EQ per channel, as well as bass, treble and DC blocking. External clocking can be provided at 4 different ratios of the input sample frequency. All sample frequencies are upsampled for processing. Each internal processing channel can receive any input channel, allowing flexibility and the ability to perform active digital crossover for powered loudspeaker systems. The serial audio data interface accepts many different formats, including the popular I2S format. 2 STA328 EVALUATION BOARD DESCRIPTION 2.1 SUPPLY VOLTAGE, REGULATORS The STA328 board uses 7V power regulation for logic circuitry and 10<Vcc<35 for power section of STA328 device. 2.2 S/PDIF INPUT INTERFACE The STA328 controller's data interface is serial I2S for input. The STA328-EVB input accommodates coaxial or optical S/PDIF digital audio interfaces using a digital audio receiver IC. Jumper JP1 may select either input. S/PDIF interfaces (STA120D) will support sample rates from 32KHz to 96KHz Optical S/PDIF receiver IC is SHARP GP1F31R. 2.3 DIGITAL SIGNAL PROCESSING The STA328 converts pulse code modulated, PCM, digital audio input signals into Pulse-Width Modulated (PWM) at high level of power. The STA328 has two independent volume control registers that have an adjustment range from +48dB to -78dB in 0.5dB increments. In addition, the mater volume is adjustable from 0dB to -127dB in 0.5dB steps. Tone control registers boost or cut the treble and bass by +/-12dB, in 2dB steps. EQ filters are IIR biquads configurable by programmable coefficients. 2.4 POWER OUTPUT The STA328 provides directly power level signals. These power level signals are applied to passive two-pole low pass filter, and provide low disAN2032/0705 Rev. 1 1/10 AN2032 APPLICATION NOTE tortion audio power to the load. The output filter functions to prevent unwanted high frequency switching signals from reaching the load. Filter designs for 4Ω. Peak voltage on power pins must not exceed 35V. Snubber networks are employed to protect the output MOSFETs from inductive transients, which can reach levels higher than the supply voltage. Output snubbers are R11/C21 and R17/C32. The other critical components for device reliability are C15, C26 (1uF) and C18, C27 (100nF); these bypass capacitors from Vcc and power GND pins of STA328. These capacitors must be X7R Ceramic or Tantalum SMD construction and must be located as close as possible to the device pins. The STA328 shuts down when it reaches 150°C. 2.5 JUMPERS CONNECTOR The STA328 provides some jumpers to configure the board. JP1 (OPTIC- SPDIF -ELEC): short the central pin with ELEC pin to use Optical S/PDIF; short the central pin with OPTIC pin to use the coaxial S/PDIF (sorry for the confusion!); 2.5.1 CONNECTORS: J1: Male 20 pin connector for plug control board J2: Logic supply (5V) J3, J4, J5, J6: SMB connector; J7: Optical S/PDIF SHARP GP1F31R J8: RCA connector electric S/PDIF J9: Power Supply (10V to 35V) J10: Connector for output load A J11: Connector for output load B 3 CONFIGURE STA328-EVB WITH LPT INTERFACE 1) 2) 3) 4) 5) 6) Plug the LPT Interface on STA328 board utilizing J1 of STA328 and J2 of LPT Interface; Connect PC parallel port to the LPT board using a parallel cable; Select S/PDIF Input mode (electric or optical) with JP1; Connect output load on J10 and J11; Turn on the board; Run STA328 ControlPanel.exe on the PC. 3.1 Configuring GUI Software: 1) Go to "Registers" page on GUI. 2) Click "AutoFind LPT" button. It appears the number of LPT port (0x278 or 0x378); 3) Click "Reset" button 4) Click "Power Up" button 5) Read the register 5. The default value must be "5C" 6) Click "Test Board I/O". If "passed" it is OK. If "failed", then perform manual board-reset by press- 2/10 AN2032 APPLICATION NOTE ing SW1 button and try again. If still "failed" then make sure connections are OK. 7) Go to "Control" page on GUI. 8) Click "Ext Amp Power Up" to enable the output power. 9) Increase "ALL" master volume control. 4 PERFORMANCES 4.1 THD+Noise ratio versus output power with different PLL filters Vcc=25V; Output load = 8ohm; Input frequency = 1KHz Figure 1. Audio Precision 10 5 2 1 0.5 % 0.2 0.1 0.05 0.02 0.01 10m 20m 50m 100m 200m 500m 1 W 2 5 10 20 50 90 Vcc=25V; Output load=8 ohm; Input frequency=1KHz Red: C37=120pF; C38=1000pF; R18=7K5 Blue: C37=20pF; C38=1000pF; R18=7K5 Cyan: C37=120pF; C38=1000pF; R18=3K9 Green: C37=220pF; C38=1000pF; R18=3K9 Magenta: C37=320pF; C38=1000pF; R18=3K9 Yellow: C37=220pF; C38=1200pF; R18=3K9 4.1.1 Conclusion: Correct choice for PLL filter (for commercial component values) is: C37=220pF; C38=1200pF; R14=3.9KΩ. These values are not modified on the attached schematic. 3/10 AN2032 APPLICATION NOTE 4.2 THD+Noise ratio versus output power with different input power supply (All channel ON) Vcc=16V; Output load = 8Ω; Input frequency = 1KHz; Channel 1 and 2: ON Figure 2. Audio Precision 10 5 2 1 0.5 % 0.2 0.1 0.05 0.02 0.01 100m 200m 500m 1 2 5 10 20 50 90 W Vcc=20V; Output load=8 ohm; Output Power=1W Channel 1 ON; Channel 2 ON PLL Fi lter: C37=220pF; C38=1200pF; R18=3K9 Red: 15V; Blue: 20V; Cyan: 25V; Green: 30V; Yellow: 35V 4.3 THD+Noise ratio versus output power with different input power supply (Only channel 1 ON) Vcc=25V; Output load = 8Ω; Input frequency = 1KHz; Channel 1 ON, Channel 2 OFF Figure 3. Audio Precision 10 5 2 1 0.5 % 0.2 0.1 0.05 0.02 0.01 100m 200m 500m 1 2 5 W Output load=8 ohm; Input frequency=1KHz PLL Filter: C37=220pF; C38=1200pF; R18=3K9 Red: 15V; Blue: 20V; Cyan: 25V; Green: 30V; Magenta: 35V 4/10 10 20 50 90 AN2032 APPLICATION NOTE 4.4 Noise Floor Vcc = 25V; Output load = 8Ω; Figure 4. Audio Precision +0 -20 -40 d B r A -60 -80 -100 -120 -140 20 50 100 200 500 1k 2k 5k 10k 20k Hz Vcc=25V; Output load=8 ohm; Output Power=-60dB Channel 1 ON; Channel 2 OFF PLL Filter: C37=220pF; C38=1200pF; R18=3K9 Figure 5. Analyzer Output Power Versus Input Power Supply Vcc = 25V; Output load = 8Ω; Input frequency = 1KHz THD+Noise ratio = 1%; & Blue: THD+Noise ratio = 10% 90 80 70 60 50 W 40 30 20 10 0 +12 +14 +16 +18 +20 +22 +24 Vdc +26 +28 +30 +32 +34 +36 Output load=8 ohm; Channel 1 ON; Channel 2 OFF PLL Filter: C37=220pF; C38=1200pF; R18=3K9 Red: THD=1% Blue: THD=10% 5/10 AN2032 APPLICATION NOTE 5 SCHEMATIC AND LAYOUT 5.1 Schematic Figure 6. Power Section 5V LD1086DT50 GND J2 + 2 C3 10u 10V + C1 22u 10V IN GND 1 C4 100nF 1 Logic OUT GND +7V IN 3 3A3 LD1086DT33 U2 2 OUT L1 FERRITE 2 C5 100nF 1 U1 3 3V3 C2 10u 10V + C6 100nF FERRITE L2 J1 0 2 R3 1 R2 J3 DATA DATA SPDIF DATA 0 SDA J4 BICKI 3V3 BICKI SPDIF 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 TM PAR RESET 1 2 SCL BICKI R1 0 2 R5 1 R4 J5 LRCKI LRCKI SPDIF LRCKI 0 J6 XTI 0 SCAN OUT 1 2 XTI SPDIF XTI 3V3 5V CON20 Figure 7. S/PDIF Section U3 3V3 1 2 5V L3 C7 100nF R6 0 3 4 FERRITE J7 GP1F31R +VS GND DATA 5 100nF 6 C8 7 1 2 3 8 C10 100nF 9 JP1 1 3 10 OPT 2 ELEC 11 C13 12 100nF 13 SPDT/SM J8 R9 82 14 C VERF Cd/F1 Ce/F2 Cc/F0 SDATA Cb/E2 ERF Ca/E1 M1 C0/E0 M0 VD+ VA+ DGND FILT RXN MCK FSYNC SCK BICKI SPDIF U CBL 0 3V3 6/10 M3 SEL STA120 R10 M2 CS12/FCK RCA JACK LRCKI SPDIF AGND RXP 28 27 26 25 24 DATA SPDIF D1 R23 3V3 560 LED 23 22 C9 21 100nF 20 19 3A3 330 XTI SPDIF R7 C11 15nF C12 470nF 18 17 R8 16 15 3V3 0 AN2032 APPLICATION NOTE Figure 8. STA328 Section LRCKI R19 0 VCC 2 1 J9 R21 0 NS STA328 C16 SCAN OUT 100nF 3V3 C20 BICKI 100nF LRCK I/O DATA 3V3 C25 PLL_FILT 100nF XTI TM SDA SCL RESET 3V3 R14 10K 3V3 C28 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 U4 VccSig NC Vss NC Vdd OUT2B GND Vcc2B BICKI NC LRCKI GND2B SDI GND2A Vdd Vcc2A GND OUT2A XTI OUT1B PLL FILTER Vcc1B nc GND1B SDA GND1A SCL NC RESET Vcc1A CONFIG OUT1A Vd GND_Clean Vdd GND_Reg 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 OUT2B C15 1uF C18 100nF C23 OUT2A OUT1B + LRCK I/O 2200uF 50V C26 1uF OUT1A C27 100nF 100nF SW1 C29 1nF RESET C30 100nF PLL_FILT R18 R20 TM 0 NS TM PAR R22 7K5 C37 20pF 0 C38 470pF Figure 9. Output Filter Section OUT1B L6 22uH OUT2B L4 22uH C14 C31 100nF C32 R16 R17 22 C36 100nF OUT1A L7 R15 6 330pF 22uH 6 C33 100nF C35 100nF R11 22 J11 C34 470nF 100nF 2 1 C21 RIGHT 330pF OUT2A R12 6 R13 C24 6 C17 100nF J10 C19 470nF C22 2 1 LEFT 100nF 100nF L5 22uH 7/10 AN2032 APPLICATION NOTE 5.2 Layout Figure 10. Component Layer Figure 11. Solder Layer Figure 12. Serigraphy 8/10 AN2032 APPLICATION NOTE Table 1. Revision History Date Revision July 2005 1 Description of Changes First Issue 9/10 AN2032 APPLICATION NOTE The present note which is for guidance only, aims at providing customers with information regarding their products in order for them to save time. As a result, STMicroelectronics shall not be held liable for any direct, indirect or consequential damages with respect to any claims arising from the content of such a note and/or the use made by customers of the information contained herein in connection with their products. Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners © 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 10/10