ATMEL AVR®32 UC3A Series

ATMEL AVR®32 UC3A Series
The World's Lowest Power 32-bit Flash MCU with Ethernet and USB On-The-Go
80 Dhrystone MIPS and Draws Only 40 mA at 66 MHz
The AVR®32 UC3A Series – based on Atmel® AVR32 UC core – feature a 512K bytes Flash, an
embedded 10/100 Ethernet MAC, a full-speed (12 Mbps) USB 2.0 with on-the-go (OTG) capability and
an SRAM/SDRAM external bus interface.
The AT32UC3A0512 and AT32UC3A1512, the first devices available, deliver 80 Dhrystone MIPS
(DMIPS) at 66 MHz and consume only 40 mA at 3.3V. The power consumption, as low as 1.65
mW/DMIPS, outperforms by a ratio of 1.7 to 4.3 other available architectures offering similar feature sets
and lower processing performances. The standby power consumption of UC3A Series is just 40 microAmps.
The AVR32 UC core is the second core to be based on Atmel's AVR32 architecture, la unched in 2006. It
has single cycle DSP instructions that include multipliers and multiply-and-accumulate, and executes 1.3
DMIPS/MHz.
Acte Oy
Larin Kyöstin tie 4 FI-00650 Helsinki • PL 36 FI-00641 Helsinki
Tel.: +358 (0)9 75 2761 • Fax.: +358 (0)9 7527 6660
www.acte.fi shop.acte.fi [email protected]
Dual-bank pipelined Flash delivers single-cycle instructions – In contrast to other MCUs, the AVR32
UC core, system bus matrix, memory subsystem and peripherals were designed from the ground up, as a
whole, to ensure optimum performance. The AVR32 UC core was designed specifically to interface to onchip Flash memories. The Flash on UC3A Series devices uses a pipelined, dual-bank architecture that
outputs one word every clock cycle when executing sequential code, with or without a wait state.
Employing a wait-state allows microcontrollers clock frequency to be increased from 40 MHz to 66 MHz,
and results in a negligible reduction in per cycle throughput of only 8% - from1.3 to 1.2 DMIPS/MHz.
Six Layer Bus Architecture with Dynamic Frequency Scaling – UC3A Series MCUs have a six-layer
high speed bus matrix with point-to-point connections from all masters to all slaves, enabling masters to
concurrently access any slave at a maximum speed of 264M bytes per second at 66 MHz. If multiple
masters wish to access the same slave, arbitration is automatically performed. The bus masters in UC3A
Series devices are the AVR32 UC core data and instruction interfaces, peripheral DMA controller, and
several high speed peripherals such as the Ethernet MAC and USB. The bus slaves are the on-chip SRAM
and Flash memories, USB, the two peripheral bus bridges, and the external bus interface (EBI).
Peripheral DMA Controller Ensures up to 24M bytes per Second Data Transfer at 66 MHz – The 15
channel peripheral DMA controller on the UC3A Series connects each peripheral directly to the entire
addressable memory system, enabling high bandwidth data transfers without any processor overhead.
Conventional processors, which require the CPU to transfer data one byte at a time, consume 55% of their
processing resources at just 250K bytes/s and 100% of it at 500K bytes/s. The peripheral DMA on UC3A
Series MCUs provides 15 DMA channels with a total available bandwidth of 24M bytes/s.
Peripheral Set Matches that of Atmel's ARM-based Controllers – The UC3A Series MCU family
utilizes many of the same features Atmel developed for its SAM7 and SAM9 families of ARM-based
MCUs including the peripheral DMA controller, multi-layer high speed bus architecture, Ethernet MAC,
analog to digital converter and serial communication peripherals.
The UC3A Series MCUs features Ethernet and USB and target networking embedded applications. The
UC3B Series offer USB connectivity and lower pin-count targeting PC-centric embedded applications.
Both are especially suited for portable devices thanks to the excellent consumption/performance ratio.
Acte Oy
Larin Kyöstin tie 4 FI-00650 Helsinki • PL 36 FI-00641 Helsinki
Tel.: +358 (0)9 75 2761 • Fax.: +358 (0)9 7527 6660
www.acte.fi shop.acte.fi [email protected]