Concerto™ College

Concerto™ College
Topic 10: Operating Systems
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Agenda
•  SYS/BIOS Overview
–  APIs
–  Development Support
–  Benchmarks
•  Multi-Core Support for Concerto
–  SYS/BIOS and SYS/BIOS IPC
(interprocessor communication
product) run on both the M3 and
28x
–  Notify and MessageQ for
communication between threads on
both cores
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SYS/BIOS 6.x Real-Time Operating System
•  SYS/BIOS is an open-source RTOS for TI Embedded Processors
–  BSD licensed: all source code included with build support
–  Free: no development or runtime licensing costs
–  Integrated with TI s IDE, CCS/Eclipse
•  Portable
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ARM: Cortex M3, A8, ARM926
C2000 DSC Family
MSP430 MCU Family
C6000 DSP Family
•  High Performance
–  Minimal interrupt latency, fast context switch, multiple thread levels
–  Memory efficient for both code and data
•  Scalable
–  From small, static kernel-only to dynamic, multi-core networked systems
–  Additional packages for IPC, TCP/IP, filesystems, multimedia frameworks
•  Modular and Extensible
•  Latest generation in a family of RTOS products going back 20 years
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SYS/BIOS Architecture
I/O
MessageQ
Stream
TCP/IP Network
Filesystem
Sockets
FatFS
Kernel
Clock
Event
Semaphore
Mailbox
Cache
Timer
Hwi
Timestamp
Log
Diags
Swi
Task
Gate
Startup
HAL
Runtime
Memory
System
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API Design
•  Consistent design pattern followed for all modules
–  Ease-of-use: Learn the mechanics for one module, and the rest will follow
•  Supports both dynamic and static creation of objects (instances)
–  Static: create object with configuration tool at build time – saves code/data
–  Dynamic: create object with application C code at runtime
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Low-level Runtime Services
•  Memory
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Pluggable memory management
Multiple co-resident managers possible
Traditional malloc style, pools, and alloc-only implementations supplied
Users can write application-specific allocators and easily integrate
•  Log
–  Efficient mechanism for capturing events in application and SYS/BIOS
–  Host tools provided to view log events
–  Includes a printf() functionality where the formatting happens on development host
•  Startup
–  Handles initialization of CPU and stack
–  Enables custom startup functions to be run before main()
•  System
–  Low level system services (printf-style output, abort, etc)
•  Gate
–  Mutual exclusion
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Threading Model
•  SYS/BIOS defines four types of threads
–  Thread – an independent, schedulable execution context
–  For an RTOS, what priority and context (stack, registers) are provided for a thread are
key attributes
–  SYS/BIOS is a preemptive, priority based scheduler
•  Idle (background) thread
–  Lowest priority and runs when nothing else is ready
–  Can be eliminated and have the processor sleep
•  Task thread
–  Traditional independent stack and priority thread – multiple priority levels
•  Software Interrupt (Swi) thread
–  Run-to-completion (non-blocking) thread with shared stack
•  Hardware Interrupt (Hwi) thread
–  Interrupt Service Routine (ISR)
–  Priorities based on device hardware characteristics
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Hardware Abstraction Layer (HAL)
•  Timer
–  Manages timer peripherals consistently across diverse implementations
–  Generates one-shot or continuous callbacks at specified rate
•  Hardware Interrupts (Hwi)
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Manages hardware interrupts that need to interact with SYS/BIOS kernel
Plug ISR in a device-independent way and enable/disable
ISR s can (should) be written in C
Bare-metal ISR s can be used as long as they do not call SYS/BIOS
services
•  Timestamp
–  APIs read timestamp value for logging and benchmarking
–  For Concerto, we use the common shared counter which can be read by
both the M3 and 28x
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Kernel
•  Swi (Software Interrupt)
–  Shared stack, non-blocking (run-to-completion) thread
–  Preemptible via priorities, with a configurable number of priorities
•  Task
–  Independent stack, blocking thread
–  Preemptible via priorities, with a configurable number of priorities
•  Semaphore
–  Both binary and counting varieties
–  Support for preventing priority inversion
•  Event
–  Enables waiting for multiple synchronization objects (ala select() )
•  Clock
–  Provides either one-shot or periodic Swi-level callbacks
•  Hook functions enable custom actions during context switches for Hwi, Swi,
and Task objects
–  Example: Optional stack overflow check during each Task context switch
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Development Support
•  CCS/Eclipse and command-line tools
•  Windows and Linux
•  Utilizes TI compiler toolchains
–  Support for other vendor toolchains under development
•  Configuration tool
•  IDE Integration
–  Searchable Help
–  Supports CDT Features: auto-completion, hover-help
–  Custom examples generated from New Project Wizard
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Configuration
•  Configuration enables users to generate a customized, optimized RTOS
tailored for their applications
•  Configuration is used for:
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Specifying which SYS/BIOS modules will be used
Setting module options to change their run-time behavior and properties
Creating static kernel objects (Task, Semaphore, Swi) at build-time
Performing integrity checks among interdependent modules
•  Configurations can be shared or re-used across many applications, or be
unique for each application
–  Shared: generate once and link to many applications
–  Unique: even application-specific configurations can include common settings
•  Configurations are specified using JavaScript
–  Edit using custom GUI editor integrated in CCS/Eclipse
–  Edit directly using favorite programmer s editor
•  Buildable via CCS/Eclipse projects or via command-line in makefile s
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Graphical Configuration Tool
Navigate included
modules and objects
Double-click to
start editor
Switch between
graphical view and
source view
Lists errors/warnings
detected during build/
validation
Choose which
features to
include
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Debug Support
•  Object Viewer (ROV) provides higher-level view of internal state of objects like
Task, Swi, and Semaphore
–  Smart Watch Window – much more than a raw C struct view
–  Example: stack and heap usage computed and displayed
•  Instrumentation (Real-Time Analysis, RTA)
–  Interesting events are efficiently logged from SYS/BIOS and application code
–  Host tools decode and display: context-switch graph, CPU load, status messages
•  Exceptions
–  Hardware-generated exceptions are caught and context is saved (ISA-specific)
•  Stack checking at runtime
•  Debug kernel
–  Parameter checking via asserts
–  Internal state asserts
–  Optional via configuration – no API differences
•  Source code
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Object Viewer (ROV)
•  ROV provides four different views
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Module: module-wide (global) state
Basic: simpler view of state for each object (instance)
Detailed: advanced view of state for each object
Raw: all the state in an unfiltered view (much like a C struct view)
•  Runs in the same Debug perspective as C source debugger
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RTA Block Diagram
Desktop Host
Data Visualization
Toolkit
(Eclipse-based)
ROV
decoder
RTA
decoder
Target
Target Server
Instrumented
Application & OS
JTAG (stop-mode) or
Ethernet (UDP) or
UART or
Ethernet
Microprocessor
Shared
Memory
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Host
Channel
Options
Buffer
RTA
agent
Buffer
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28x Features
•  Minimal-Latency Interrupt Mode
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Hwi Interrupt Manager can be configured to use IER to disable interrupts
Hwi_disable/restore adjust bits in IER and never touch INTM
Interrupt dispatcher adjusts IER and reenables INTM within ~35 instructions
Caveats
•  Minimal-latency interrupt routines cannot make any BIOS system calls
•  Minimal-latency mode has slightly higher overhead since IER bits are harder to
manage than INTM bit
•  Does not support minimal and non-minimal ISR in same PIE group
•  Support for PIE
–  Hwi_create() intrId parameter maps to PIE id
•  0-31 map to core interrupts and traps
•  32-127 map to PIE interrupts (12 groups of 8)
–  Dispatcher does necessary ACK for PIE group
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Cortex-M3 Features
•  Zero-latency interrupt disable option
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Max interrupt disable priority is specified at configuration time
Hwi_disable() raises priority only to this level
Allows ISRs of higher priority to preempt BIOS critical regions
Zero-latency ISRs cannot make BIOS system calls
•  Exception Handler
–  Dumps entire register context to CCS and memory buffer for ROV
–  Helps to quickly identify reason for hardware exceptions
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Concerto Features
•  Timestamp module reads shared timestamp counter so that timebase is
the same on both cores.
•  Multi-core support (described later)
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Timing Benchmarks
•  Benchmark data is updated and provided with each product release. Check
your product documentation for corresponding benchmarks.
28x
M3
Interrupt Latency (using minimal Hwi config)
156 (35)
82 (0)
Interrupt to Software Interrupt (Swi)
453
379
Interrupt to Blocked Task
606
553
Semaphore pend with Task Switch
301
306
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Size Benchmarks
28x
M3
ROM
RAM
ROM
RAM
Static Semaphore/Task Application
10964
3736
8596
4332
Dynamic Semaphore/Task Application
13446
7838
9752
8468
•  All sizes below are in 8-bit bytes for comparison
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Multi-Core Support
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Multi-Core Support for Concerto
Control-28x
Host-M3
Task or Swi
MessageQ
SYS/BIOS-IPC
SYS/BIOS-IPC
SYS/BIOS
SYS/BIOS
•  We provide 2 Modules to support communications between cores
–  MessageQ for sending variable sized messages
–  Notify is a lower-level interface that supports sending 32-bit word between
cores
•  Both modules use a circular buffer in shared memory and inter-core
interrupts
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Circular Buffers (1 writer, 2 readers)
M3 Write Memory
Circular Buffer
Host-M3
Local Memory
Instance state
*putBuffer
*putWriteIndex
*putReadIndex
*getBuffer
*getWriteIndex
*getReadIndex
…
Control-28x
WriteIndex
ReadIndex
28x Write Memory
Local Memory
Instance state
*putBuffer
*putWriteIndex
*putReadIndex
*getBuffer
*getWriteIndex
*getReadIndex
…
Circular Buffer
WriteIndex
ReadIndex
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Notify Module Overview
•  Notify manager handles multiplexing/ demultiplexing of multiple interrupt
events using a single interrupt line
•  Callback function gets passed procId, eventId, arg and 32-bit payload
•  Multiple send calls will queue up the data in a circular buffer until the
receive ISR on the other side runs and drains the buffer.
–  The send API will return an error if this buffer is full.
// Called on processor that receives event
Void Notify_registerEvent(procId, lineId, eventId, cbFxn, cbArg);
// Called on processor that sends the event
Void Notify_sendEvent(procId, lineId, eventId, payload, waitClear);
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MessageQ Overview
•  Queues are created on one core and opened on same or other core
•  MessageQ_alloc() and put() are used to send messages
•  MessageQ_get() and free() are used to receive messages
•  Supports single reader, multiple writers
queue = MessageQ_create(name, params);
MessageQ_open(name, &queueId);
msg = MessageQ_alloc(heapId, size, &eb);
MessageQ_free(msg);
status = MessageQ_put(queue, msg, &eb);
status = MessageQ_get(queue, &msg, timeout, &eb);
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Summary
•  SYS/BIOS provides a common RTOS and APIs on both Concerto cores
•  Communication between threads on different cores using Notify or
MessageQ
•  Common development environment on both cores
–  CCS/Eclipse
–  TI compiler tools, .map files, loaders, etc.
–  SYS/BIOS ROV and RTA tools for debug and analysis
•  Integrated TCP/IP, filesystem and USB support coming soon
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Thankyou for your time!
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