Correction of static mismatch errors in a D/A converter

&
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EP 1 775 838 B9
CORRECTED EUROPEAN PATENT SPECIFICATION
(12)
(15) Correction information:
(51) Int Cl.:
Corrected version no 2 (W2 B1)
Corrections, see
Description
Paragraph(s) 25, 27, 29, 31, 38
Claims DE
1-3, 6, 11-13, 16
Claims EN
1-3, 6, 11-13, 16
Claims FR
1-3, 6, 11-13, 16
H03M 1/10 (2006.01)
H03M 1/66 (2006.01)
(48) Corrigendum issued on:
03.03.2010 Bulletin 2010/09
(45) Date of publication and mention
of the grant of the patent:
02.09.2009 Bulletin 2009/36
(21) Application number: 05022150.6
(22) Date of filing: 11.10.2005
(54) Correction of static mismatch errors in a D/A converter
Korrektur von statischen Fehlern durch Fehlanpassung in D/A-Umwandlern
Correction des erreurs de désadaptation dans un convertisseur N/A
(84) Designated Contracting States:
DE
(43) Date of publication of application:
18.04.2007 Bulletin 2007/16
(73) Proprietor: Infineon Technologies AG
• Eklund, Jan-Erik
583 33 Linköping (SE)
(74) Representative: Patentanwälte Lambsdorff &
Lange
Dingolfinger Strasse 6
81673 München (DE)
85579 Neubiberg (DE)
(56) References cited:
(72) Inventors:
EP 1 775 838 B9
• Rudberg, Mikael
583 32 Linköping (SE)
US-A- 4 503 421
US-B1- 6 489 911
US-A- 4 963 870
Note: Within nine months of the publication of the mention of the grant of the European patent in the European Patent
Bulletin, any person may give notice to the European Patent Office of opposition to that patent, in accordance with the
Implementing Regulations. Notice of opposition shall not be deemed to have been filed until the opposition fee has been
paid. (Art. 99(1) European Patent Convention).
Printed by Jouve, 75001 PARIS (FR)
EP 1 775 838 B9
Description
FIELD OF INVENTION
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[0001] The present invention relates to a method, device, computer program products and a computer readable
medium for the correction of static mismatch errors in a D/A converter, where an input word, being the digital representation
of an analogue input signal, is divided into one most significant part, a msb-word, and one least significant part, a lsbword, and where said msb-word is represented by msb-bits and said lsb-word is represented by lsb-bits.
[0002] The D/A converters (DACs) of interest for the present invention is the ones that can be referred to as Nyquist
converters (i.e. we exclude the sigma-delta converters). In these DACs the output signal typically is created by switching
currents between a differential output pair (so called current steering DACs). However the invention also applies to areas
where the output signal is generated by switching capacitors or resistors.
[0003] The DACs are often divided into segments since the matching requirements between the current sources are
higher for the most significant bits of the input word. Consider for instance the 8 most significant bits in a 16 bit converter
that have a 1% error in the current. The resulting output current will be:
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which with the input (214 + 30) corresponds to:
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that is, the error is 138 lsbs.
[0004] But an error in the lsb is much more forgiving:
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i.e. 0,3 lsb.
[0005] Since the lsb sources are less sensitive to errors the DACs are often divided into two or three banks (segments)
with differently sized reference sources (current sources, resistors, capacitors).
PRIOR ART
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[0006] It is known that many DAC suppliers apply various calibration steps at the reference sources, it is for instance
known to perform laser trimming of the current sources in high performance DACs.
[0007] The document US-A-4 963 870 represents the closest prior art and relates to a D/A converting device comprising
a first D/A converter for converting upper M bits of a digital input signals into a first analog signal, a memory for receiving,
as address data, at least a digital signal of lower N bits of the input digital signal to output lower-bit-output approximate
data in response to the address data, a second D/A converter for converting digital data at least including the lower-bitoutput approximate data into a second analog signal and an analog adder for outputting an added analog signal obtained
by adding the first and second analog signals. Here, the lower-bit-output approximate data are set such that, supposing
a level change of the added analog signal with respect to a change of an lsb of the upper M bits being ∆L, a minimum
step increase of the digital signal of lower N bits causes a level of the added analog signal to increase by about ∆L/2N.
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SUMMARY OF THE PRESENT INVENTION
Problem
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[0008] The problem to be solved is to improve the accuracy of the msb-weighted references, i.e. the static matching,
in a DAC.
Solution
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[0009] A solution to the problem is to perform the correction of the DAC sources purely in the digital domain which is
easier than trying to correct analogue references directly.
[0010] The present invention teaches the introduction of some redundancy in the representation by changing the
weight of the MSB sources in a segmented DAC.
[0011] Consider a DAC with a segmentation of 8 msbs and 8 lsbs. In a conventional weighted DAC the output words
are created as
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due to the difference in size of the references (e.g. current sources). With this coding there is a unique input to output
value mapping in the DAC. The present invention introduces some redundancy by making the msb weight a little bit
smaller. One possible example would be that the weight is changed from 28 to 248 so that the output word is created as:
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[0012] With this representation some output values can be created from two different input words. One example would
be the output 252 which can be created by either
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or
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[0013] The reason for this redundancy is that one msb is worth less than the total sum of all available lsbs.
[0014] Consider that there is an error in the msb weight so that its weight is larger than the nominal value. As an
example, assume that the msb weight in reality is 253. In the example the output value 252 was wanted. This is possible
by the input word
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[0015] This shows that even if there is an error in the msb it is possible to find an input code that gives the right output
value assuming that the real or effective msb weight is known. The effective msb weight will vary depending on the input
code since a varying number of msb sources are active.
[0016] As long as the effective msb weight is below or equal to in this case 256 it is still possible to find an input code
that gives the right output code even with a deviation from the nominal value present. This is however only possible if
the effective weight is lower than the nominal one when using conventional weighting.
[0017] It is for example not possible to create the output value 256 if an error in the weight causes the effective msb
weight to be 257. The closest result is
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or
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[0018] The term used for this kind of redundancy is sub ranging. The problem that the present invention deals with is
how to recalculate the input word to the DAC once the effective msb weights are known.
[0019] The present invention teaches that the input word is calculated in different steps. First split the input word into
one lsb part, lsb-word, and one msb part, msb-word. The lsb-word is represented with lsb-bits and the msb-word with
msb-bits.
[0020] Implement two look-up tables where LUT1 contains the error in the msb-word of the input word with a given
input word. Initially assume that lsb-word is zero since this needs special handling.
[0021] That is, the corrected msb-word, c-msb-word, is given by:
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[0022]
The second LUT (LUT2) contains the lsb part of the error such as the correct output, c1-output is given as:
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[0023] Note that cl-output will contain a non-zero lsb part even if the assumption here was that the input word had
zero as lsb part.
[0024] The next step is to take care of a non-zero lsb part in the input word. When the lsb-word is non-zero the natural
thing would be to extend the above expression of c1-output to:
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[0025] However when the lsb part of the input and the correction part are added together (i.e. LUT2(c-msb-word) +
lsb-word) an additional msb might be generated. This msb is always generated when the operation runs out of available
range in the lsb-part, 2lsb-bit-1, when using conventional binary arithmetic. However, the weight of this additional msb
might be something else than 2lsb_bits since the weights intentionally have been lowered and since it can be expected
that they contain some weight error as well. Thus, since one msb is to be added with the weight of 2lsb-bits, but only a
msb weight that is somewhat lower is available, it is in reality required to add some additional lsbs to come up to the
expected 2lsb_bits.
[0026] In the above given example a newly generated msb only have the weight of 248 instead of the assumed 256.
When a new msb is generated with the settings as in the example the output from the DA converter only increase with
248 lsb instead of the assumed 256. The solution is then to add another 8 lsbs to the corrected output word.
[0027] It is however a problem to calculate the weight of the additional msb. This is simply done from the "full weight"
2lsb-bits subtracting the difference between two adjacent positions in LUT2, adjacent since maximally one additional msb
is generated, modulus the lsb-range. A corrected output is then:
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[0028] At some situations yet another msb can be generated by the expression for c2-output. Fortunately the same
correction method described by above can be applied again. So when another msb is generated another adjustment
gives the correction as:
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[0029] There are thus three different equations for c1-output c2-output and c3-output, to apply. Which ones to use is
dependent on how msbs are generated. In a proposed implementation c1-output is calculated first, it is then detected if
msb is altered and in that case c2-output or even c3-output is calculated. The complete correction method is summarized
below:
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if msb-part(cl-output) ≠ msb-part(c-msb-word) then
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if msb-part(c2-output) ≠ msb-part(cl-output) then
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[0030] The LUTs can be derived from carefully measuring the output of a D/A converter when applying a ramp at the
input and for every value measure the output current. Below there is an example in Matlab how to create the LUTs from
a measured weight deviation of each msb. In the example we assume that these values are available in some kind of
on-chip fuses (in the example stored in variable fuse). Anyone with some HW experience can easily see how to convert
this Matlab code to a hardware implementation.
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[0031] Since the msb weights are lower than the commonly used 2lsb-bits the range is somewhat lower than when
using conventional methods. The impact of this range reduction is very low, but an annoying clip effect might happen
when the use apply full range input signals. The solution to this is to scale the signal before the DAC. To avoid introducing
a DC offset when doing gain scaling it should be performed on data in 2’s complement representation. A DAC typically
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EP 1 775 838 B9
have an unsigned representation (offset binary code) as input. This conversion is easily done as an inversion of the
most significant bit. So the gain scale procedure shall be:
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offset binary code to 2’s complement conversion (not needed if already in 2’s complement representation)
data-out = data-in * gain
perform correction calculations as described in this invention
2’s complement conversion to offset binary code (not needed if already in 2’s complement representation)
send data to DAC.
A method, device or computer program product according to the present invention will provide the same effect as
laser trimming, but only with the use of a purely digital method. The present invention provides a purely digital
correction method and a predictable number of LUT operations making HW implementations of the algorithm efficient
BRIEF DESCRIPTION OF DRAWINGS
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[0032] A method, a device and a computer program product according to the present invention will now be described
in detail with reference to the accompanying drawings, in which:
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
is a schematic and very simplified illustration of how an input word is divided into two parts,
is a flowchart diagram on the calculation of a corrected output word,
is a flowchart diagram on how to derive a first and second look up table,
is a simplified and schematic illustration of how analogue output values are obtained,
is a flowchart diagram on how to update the first look up table,
is a flowchart diagram on how to scale the input signal,
is a simplified and schematic illustration of a first embodiment of an inventive device and a D/A converter,
is a simplified and schematic illustration of a second embodiment of an inventive device and a D/A converter,
and
is an example of a possible realisation of the present invention.
DESCRIPTION OF PREFERRED EMBODIMENTS
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[0033] A method of the correction of static mismatch errors in a D/A converter, according to the present invention, will
now be described in with reference to figure 1 and 2, showing where an input word 1, being the digital representation
of an analogue input signal, is divided into one most significant part, a msb-word 11, and one least significant part, a
lsb-word 12, being the first step 21 in figure 2. The msb-word 11 is represented by msb-bits 111, 112, 11m and the lsbword 12 is represented by lsb-bits 121, 122, 12m.
[0034] The second step, 22, according to the present invention is that the effective weight of the least significant msbbit 111 is set to be less than the total sum of all lsb-bits, 121+122+...+12m.
[0035] The next step, 23, of an inventive method is to implement a first look up table, LUT1, containing the most
significant part of the error, so that a corrected msb-word, c-msb-word, would be equal to the msb-word plus a value in
LUT1 representing the msb-word.
[0036] The next step, 24, is to implement a second look up table, LUT2, containing the least significant part of the
error, so that a first corrected output, c1-output, would be equal to c-msb-word plus a value in LUT2 representing said
c-msb-word added to said lsb-word.
[0037] It is possible that a most significant bit has to be added to the first corrected output, c1-output, in order to
compensate for the lower effective weight of the msb-word. The present invention teaches, in the following step 25, that
if the most significant part of c1-output differs from the most significant part of c-msb-word, then a first compensation is
required.
[0038] The next step 26 according to the invention teaches that this compensation is calculated by setting a second
corrected output, c2-output, to be equal to c1-output plus the least significant bit range, 2 lsb-bits minus the difference
between the values in two adjacent positions in LUT2 modulus 2lsb-bits.
[0039] At some situations yet another most significant bit can be generated by step 26, fortunately this can be corrected
in the same way as described above. Thus the next step 27, shows that if the most significant part of c2-output differs
from the most significant part of c1-output, then a second compensation is required.
[0040] The next step 28 according to the present invention teaches that a third corrected output, c3-output, is set to
be equal to c2-output plus the least significant bit range, 2lsb-bits, minus the difference between the values in two adjacent
positions in LUT2 modulus 2lsb-bits.
[0041] As can be seen in step 26, it is proposed that the difference between the values in two adjacent positions in
LUT2 when calculating the first compensation is set to be the difference between the value in the position representing
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c-msb-word and the value in the position representing c-msb-word +1.
[0042] As can be seen in step 28, it is proposed that the difference between the values in two adjacent positions in
LUT2 when calculating the second compensation is set to be the difference between the value in the position representing
c-msb-word +1 and the value in the position representing c-msb-word +2.
[0043] In order to enable a correction according to the present invention it is essential to set up the two look up tables
LUT1, LUT2.
[0044] Figure 3 is a schematic flowchart diagram showing a possible way to derive LUT1 and LUT2. The first step 31
is to set all values in LUT1 and LUT2 to zero and setting a value for parameter n to zero.
[0045] The tables will now be calculated for positions in the tables corresponding to digital values in the range from
1 to m, m being the highest value in the least significant bit range.
[0046] The next step 32 is to increase the value for parameter n with 1.
[0047] The next step 33 is to set the error, or deviation of an output value, DEVn, to be the difference between the
expected output value, EXPn, and an actual weight for a specific digital input value, ACTn, where the expected output
value, EXPn, is equal to n times m, and the actual weight, ACTn, is the difference between the least significant bit range,
2 isb-bits and an analogue output value OP(n+1), which analogue output value OP(n+1) is the analogue output coming
from the D/A converter as a response to a digital input value IP(n+1).
The following step 34 indicates that the value in position n+1 of LUT1 is set to be the most significant bits of DEVn, and
the step after that indicates that the value in position n+1 of LUT2 is set to be the least significant bits of DEVn.
[0048] In step 36 it is checked if n has been stepped all the way up to m-1, if not steps 32 to 35 are repeated, if n=m1 then the look up tables are derived.
[0049] Figure 4 shows schematically that the analogue output values OPn can be obtained by applying a ramp of
digital input values IPn at the input of the D/A converter A, and measuring the analogue output value, OPn, for every
digital input value, IPn, for every n in the range of 1 to m-1.
[0050] It is proposed that the analogue output values OPn are measured and stored in means for information storage,
thus being available for later retrieval and use when deriving the first and second look up tables, LUT1, LUT2.
[0051] In order to save memory access it is proposed that the first look up table is updated one more time. Figure 5
shows schematically that this is done by, for every n in the range of 1 to m-1.
[0052] A first step 51 is to set n to be zero, and a second 52 step is to set n to be n+1.
[0053] The next step 53 is to store the value of position n+1 of LUT1 in a first storage element tmp1.
[0054] The next step 54 is to store the sum of the value of said first storage element tmp1 and n in a second storage
element tmp2.
The next step 55 is to check if the value in the second storage element tmp2 is smaller than 2msb-bits-1, and if so then
to go to the following step.
[0055] The next step 56 is to store the value in LUT1 representing the value in said second storage element +1 in a
third storage element tmp3.
[0056] The next steps 57 is to check if the value in the first storage element tmp1 is not equal to the value of the third
storage element tmp3, and if so then go to the next step.
[0057] The next step 58 is to set the value of position n+1 in LUT1 to the value of the third storage element tmp3.
[0058] The next step 59 is to check if n has been stepped all the way up to m-1, if not steps 52 to 58 are repeated, if
n=m-1 then the look up tables has been updated.
[0059] It might be required to scale the input signal to the D/A converter, data-in, to an adapted input signal, dataadapted, by a gain factor. Figure 6 shows schematically that this can be one through the following steps.
[0060] A first step 61 is to check if the input signal is in 2’s complement representation, if not, then go to next step, if
it is, then go to step 63.
[0061] The next step 62 is to offset the binary code of the input signal to 2’s complement conversion.
[0062] The next step 63 is to set data-adapted to data-in times the gain factor.
[0063] The next step 64 is to perform correction calculations according to the invention.
[0064] The next step 65 is to check if the input signal was in 2’s complement representation, if not, then go to next
step, if it was, then go to step 67.
[0065] The next step 66 is to 2’s complement conversion to offset binary code.
[0066] The last step 67 is to send data to the D/A converter.
[0067] The present invention also relates to a device for the correction of static mismatch errors in a D/A converter.
This device will now be described with renewed reference to figure 1 and 2, showing that the device is adapted to divide
an input word 1, being the digital representation of an analogue input signal, into one most significant part, a msb-word
11, and one least significant part, a lsb-word 12, step 21, where the msb-word 11 is represented by msb-bits 111, 112,
11m and the lsb-word 12 is represented by lsb-bits 121, 122, 12m.
[0068] Figure 7 shows a D/A converter A where the input signal IP is sent to the D/A converter A through an inventive
device B. The device B is adapted to recalculate the input signal IP so that a corrected input signal IPc is sent to the
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D/A converter, where the corrected input signal IPc will give a corrected analogue output signal OPc that corresponds
to the original input signal IP.
[0069] The inventive device B is adapted to set the effective weight of the least significant msb-bit to be less than the
total sum of all lsb-bits, step 22.
[0070] The device B comprises a first look up table, LUT1, and a second look up table, LUT2, where the first look up
table contains the most significant part of the error, enabling the device to produce a corrected msb-word, c-msb-word,
that is equal to the msb-word plus a value in LUT1 representing the msb-word, step 23, and that the second look up
table contains the least significant part of the error, enabling the device to produce a first corrected output, c1-output,
that is equal to c-msb-word plus a value in LUT2 representing the c-msb-word, all of this added to the lsb-word, step 24.
[0071] The present invention teaches that if the most significant part of c1-output differs from the most significant part
of c-msb-word, step 25, then the inventive device is adapted to set a second corrected output, c2-output, to be equal to
c1-output plus the least significant bit range, 2lsb-bits, minus the difference between the values in two adjacent positions
in LUT2 modulus 2 lsb-bits step 26.
[0072] The present invention also teaches that if the most significant part of c2-output differs from the most significant
part of c1-output, step 27, then the inventive device is adapted to set a third corrected output, c3-output, to be equal to
c2-output plus the least significant bit range, 2lsb-bit, minus the difference between the values in two adjacent positions
in LUT2 modulus 2lsb-bits, step 28.
[0073] As it is shown in step 26, it is proposed that the device can be adapted to calculate the difference between the
values in two adjacent positions in LUT2 to be the difference between the value in the position representing c-msb-word
and the value in the position representing c-msb-word +1 in the calculation of the second corrected output, c2-output.
[0074] As it is shown in step 28, it is proposed that the device is adapted to calculate the difference between the values
in two adjacent positions in LUT2 to be the difference between the value in the position representing c-msb-word +1
and the value in the position representing c-msb-word +2 in the calculation of the third corrected output, c3-output.
[0075] An inventive device may be set up to correct the static mismatch error from a specific D/A converter according
to the flowchart diagram of figure 3, showing the steps of for every n in the range of 1 to m-1, steps 31, 32 and 36, m
being the highest value in the least significant bit range, where the value in position n+1 of LUT1 is the most significant
bits of DEVn, step 34, where the value in position n+1 of LUT2 is the least significant bits of DEVn, step 35, where DEVn
is the difference between the expected output value, EXPn, and an actual weight for a specific digital input value, ACTn,
step 33.
[0076] The expected output value, EXPn, being equal to n times m, and the actual weight, ACTn, being the difference
between the least significant bit range, 2lsb-bits, and the analogue output value OP(n+1), which analogue output value
OP(n+1) is the analogue output coming from a specific D/A converter as a response to a digital input value IP(n+1).
[0077] The analogue output values for OPn for the specific D/A converter A may be retrieved from different sources.
One proposed embodiment shows that the device B comprises means for information storage B1, such as on-chip fuses,
where the analogue output values, OPn, are stored and available for the deriving of the first and second look up table,
LUT1, LUT2.
[0078] It is also possible that the D/A converter A’, as shown in figure 8, comprises means for information storage A1,
such as on-chip fuses, where the analogue output values, OPn, are stored and available for the deriving of the first and
second look up table, LUT1, LUT2 by a device B’.
[0079] The present invention shows that the device A may be adapted to update LUT1 one more time according to
the flowchart diagram of figure 5, showing the steps of, for every n in the range of 1 to m-1, steps 51, 52 and 59,
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[0080] The present invention also shows that an inventive device may be adapted to scale the input signal to the D/A
converter, data-in, to an adapted input signal, data-adapted, by a gain factor, the device thus being adapted to;
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store the value of position n+1 of LUT1 in a first storage element, step 52,
store the sum of the value of said first storage element and n in a second storage element, step 54,
if the value in said second storage element is smaller than 2msb-bits-1, then store the value in LUT1 representing
the value in said second storage element + 1 in a third storage element, steps 55 and 56, and
if the value in said first storage element is not equal to the value of said third storage element, then set the value of
position n+1 in LUT1 to the value of said third storage element, steps 57 and 58.
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offset the binary code of the input signal to 2’s complement conversion if the input signal is not in 2’s complement
representation, steps 61 an 62,
set said data-adapted to data-in times said gain factor, step 63,
perform the inventive correction calculations, step 64,
2’s complement convert to offset binary code if the input signal was not in 2’s complement representation, steps 65
and 66, and
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send the data to D/A converter, step 67,
according to the flowchart diagram of figure 6.
[0081] An implementation example will now be presented with reference to figure 9 showing the recalculation of words
for weights errors in msbs. Since the invention only considers the recalculation, the implementation example only covers
this case.
[0082] In figure 9 an example realising the invention is shown. The input 91 is in 16 bit offset binary code. The clip
condition 92 is set to clip if input require more than 16 bit or if the overflow flag is set. It should be noticed that LUT2 is
organised as two RAMs each two words wide. In this way it is possible to by one table look up, look up LUT2(c-msbword), LUT2(c-msb-word+1), and LUT2(c-msb-word+2).
[0083] The LUT2 address logic algorithm is:
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If the LUT2 table address (lsb-addr<7:0>) bit 1 is zero the value of
LUT2(c-msb-word) is in LUT2-RAM1(lsb-addr<7:1>) and LUT2-RAM2 contains LUT2(c-msb-word+2) and possibly
LUT2(c-msb-word+1) .
If lsb-addr<1> is one the value of LUT2(c-msb-word) is in LUT2 - RAM2(lsb-addr<7:1>) and at least the
LUT2(c-msb-word+2) is found in lsb-addr<7:1>+1.
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[0084]
The table below lists all possible cases using our example configuration again.
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Table2 Address generation of LUT2.
lsb-addr<1:0>
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where to find LUT2(c-msb-
word)
where to find LUT2(c-msb-
word + 1)
where to find LUT2(c-msb-word
+ 2)
00
RAM1 address lsb-addr<7:1>
bits 15:8
RAM1 address lsb-addr<7:1>
bits 7:0
RAM2 address lsb-addr<7:1>
bits 15:8
01
RAM1 address lsb-addr<7:1>
bits 7:0
RAM2 address lsb-addr<7:1>
bits 15:8
RAM2 address lsb-addr<7:1>
bits 7:0
10
RAM2 address lsb-addr<7:1>
bits 15:8
RAM2 address lsb-addr<7:1>
bits 7:0
RAM1 address lsb-addr<7:1>
+1 bits 15:8
11
RAM2 address lsb-addr<7:1>
bits 7:0
RAM1 address lsb-addr<7:1>
+1 bits 15:8
RAM1 address lsb-addr<7:1>
+1 bits 7:0
[0085] It is proposed that in order to get the addresses in right order for the recalculation the output from the look up
in LUT2 may be sorted in address order.
[0086] It should be understood that the present invention also may be implemented as a computer program. Hence
the present invention also relates to a computer program product comprising computer program code, which, when
executed by a computer, will enable the computer to perform a correction of static mismatch errors in a D/A converter
according to the inventive method.
[0087] An inventive computer program product 7 may also comprise computer program code 7a, which, when executed
by a computer, will enable the computer to act as an inventive device B for the correction of static mismatch errors in a
D/A converter.
[0088] The present invention also relates to a computer readable medium comprising inventive computer program code.
Claims
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1.
Method for the correction of a static mismatch error in a D/A converter (A, A’), wherein a digital input word
- comprises N bits, wherein the n-th bit, n=0,1,...,N-1, of the input word controls a contribution to an output
current of the D/A converter (A, A’), the contribution being weighted with a weight of 2n and
- is divided into one most significant part, a msb-word, and one least significant part, a lsb-word, and wherein
said msb-word is represented by m msb-bits and said lsb-word is represented by l lsb-bits, characterised in,
- calibrating the D/A converter (A, A’), such that the weight of the least significant msb-bit is set to a value smaller
than 2l,
- implementing a first look up table (LUT1) in a first unit arranged upstream of the D/A converter (A, A’), the first
10
EP 1 775 838 B9
look up table (LUT1) containing the most significant part of the error, so that a corrected msb-word, c-msb-word,
is equal to said msb-word plus a value which is chosen from the first look up table (LUT1) depending on said
msb-word, and
- implementing a second look up table (LUT2) in the first unit, the second look up table (LUT2) containing the
least significant part of the error, so that a first corrected output, c1-output, is equal to c-msb-word plus a value
which is chosen from the second look up table (LUT2) depending on said c-msb-word added to said lsb-word,
wherein a digital word output by the first unit and forwarded to the D/A converter (A, A’) comprises the first
corrected output, c1-output.
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10
2.
Method according to claim 1, characterised in that if the most significant part of c1-output differs from the most
significant part of c-msb-word, then a second corrected output, c2-output, is set to be equal to c1-output plus the
least significant bit range, 2l, minus the difference between the values in two adjacent positions in the second look
up table (LUT2) modulus 2l.
15
3.
Method according to claim 2, characterised in that if the most significant part of c2-output differs from the most
significant part of c1-output, then a third corrected output, c3-output, is set to be equal to c2-output plus the least
significant bit range, 2l, minus the difference between the values in two adjacent positions in the second look up
table (LUT2) modulus 2l.
20
4.
Method according to claim 2, characterised in the difference between the values in two adjacent positions in the
second look up table (LUT2) is set to be the difference between the value in the position representing c-msb-word
and the value in the position representing c-msb-word +1.
5.
Method according to claim 3, characterised in the difference between the values in two adjacent positions in the
second look up table (LUT2) is set to be the difference between the value in the position representing c-msb-word
+ 1 and the value in the position representing c-msb-word + 2.
6.
Method according to any preceding claims characterised in, deriving said first look up table (LUT1) and second
look up table (LUT2) by setting all values in the first look up table (LUT1) and the second look up table (LUT2) to
zero and then, for every n in the range of 1 to m-1, m being the highest value in the least significant bit range;
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30
- setting the error, or deviation, of an output value, DEVn, to be the difference between the expected output
value, EXPn, and an actual weight for a specific digital input value, ACTn, said expected output value, EXPn,
being equal to n times m, and said actual weight, ACTn, being the difference between the least significant bit
range, 2l, and an analogue output value OP(n+1), said analogue output value OP(n+1) being the analogue
output coming from said D/A converter (A, A’) as a response to a digital input value IP(n+1),
- setting the value in position n+1 of the first look up table (LUT1) to be the most significant bits of DEVn, and
- setting the value in position n+1 of the second look up table (LUT2) to be the least significant bits of DEVn. _
35
40
7.
Method according to claim 6, characterised in obtaining said analogue output values by applying a ramp of digital
input values IPn at the input of said D/A converter (A, A’), and measuring the analogue output value, OPn, for every
digital input value, IPn, for every n in the range of 1 to m-1, m being the highest value in the least significant bit range.
8.
Method according to claim 7, characterised in that said analogue output values OPn are measured and stored in
means for information storage, thus being available for later retrieval and use when deriving said first look up table
(LUT1) and second look up table (LUT2).
9.
Method according to claim 6, characterised in, updating the first look up table (LUT1) one more time, by, for every
n in the range of 1 to m-1,
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- storing the value of position n+1 of the first look up table (LUT1) in a first storage element,
- storing the sum of the value of said first storage element and n in a second storage element,
- if the value in said second storage element is smaller than 2m-1, then storing the value in the first look up table
(LUT1) representing the value in said second storage element +1 in a third storage element, and
- if the value in said first storage element is not equal to the value of said third storage element, then setting the
value of position n+1 in the first look up table (LUT1) to the value of said third storage element.
10. Method according to any preceding claims, characterised in scaling the input signal to said D/A converter (A, A’),
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EP 1 775 838 B9
data-in, to an adapted input signal, data-adapted, by a gain factor, by;
5
- if the input.signal is not in 2’s complement representation, then offset the binary code of the input signal to 2’s
complement conversion,
- set said data-adapted to data-in times said gain factor,
- perform correction calculations according to any preceding claim,
- if the input signal was not in 2’s complement representation, then 2’s complement conversion to offset binary
code, and
- send data to D/A converter (A, A’).
10
15
20
11. Device for the correction of a static mismatch error in a D/A converter (A, A’), said device being adapted to divide
a digital input word, which comprises N bits, wherein the n-th bit, n=0,1,...,N-1, of the input word controls a contribution
to an output of the D/A converter (A, A’), the contribution being weighted with a weight of 2n , into one most significant
part, a msb-word, and one least significant part, a lsb-word, where said msb-word is represented by m msb-bits and
said lsb-word is represented by l lsb-bits, characterised in, that said device is adapted to calibrate the D/A converter
(A, A’), such that the weight of the least significant msb-bit is set to a value smaller than 2l, that said device comprises
a first look up table (LUT1) and a second look up table (LUT2) that said first look up table contains the most significant
part of the error, enabling said device to produce a corrected msb-word, c-msb-word, that is equal to said msb-word
plus a value which is chosen from the first look up table (LUT1) depending on said msb-word, and that said second
look up table contains the least significant part of the error, enabling said device to produce a first corrected output,
c1-output, that is equal to c-msb-word plus a value which is chosen from the second look up table (LUT2) depending
on said c-msb-word added to said lsb-word and wherein the device is adapted to output and forward a digital word
to the D/A converter (A, A’), the digital word comprising the first corrected output, c1-output.
25
12. Device according to claim 11, characterised in that if the most significant part of c1-output differs from the most
significant part of c-msb-word, then said device is adapted to set a second corrected output, c2-output, to be equal
to c1-output plus the least significant bit range, 2l, minus the difference between the values in two adjacent positions
in the second look up table (LUT2) modulus 2l.
30
13. Device according to claim 12, characterised in that if the most significant part of c2-output differs from the most
significant part of c1-output, then said device is adapted to set a third corrected output, c3-output, to be equal to
c2-output plus the least significant bit range, 2l, minus the difference between the values in two adjacent positions
in the second look up table (LUT2) modulus 2l.
35
14. Device according to claim 12, characterised in that said device is adapted to calculate said difference between
the values in two adjacent positions in the second look up table (LUT2) to be the difference between the value in
the position representing c-msb-word and the value in the position representing c-msb-word + 1.
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50
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15. Device according to claim 13, characterised in that said device is adapted to calculate said difference between
the values in two adjacent positions in the second look up table (LUT2) to be the difference between the value in
the position representing c-msb-word +1 and the value in the position representing c-msb-word + 2.
16. Device according to any one of claims 11 to 15, characterised in that, for every n in the range of 1 to m-1, m being
the highest value in the least significant bit range, the value in position n+1 of the first look up table (LUT1) is the
most significant bits of DEVn, that the value in position n+1 of the second look up table (LUT2) is the least significant
bits of DEVn, that DEVn is the difference between the expected output value, EXPn, and an actual weight for a
specific digital input value, ACTn, said expected output value, EXPn, being equal to n times m, and said actual
weight, ACTn, being the difference between the least significant bit range, 2l, and the analogue output value OP
(n+1), said analogue output value OP(n+1) being the analogue output coming from a specific D/A converter (A, A’)
as a response to a digital input value IP(n+1), whereby said device is set to correct the static mismatch error from
said specific D/A converter (A, A’).
17. Device according to claim 16, characterised in that said device comprises means for information storage, such
as on-chip fuses, where said analogue output values, OPn, are stored and available for the deriving of said first look
up table (LUT1) and second look up table (LUT2).
18. Device according to claim 16, characterised in that the first look up table (LUT1) in said device is updated one
more time, by said device being adapted to, for every n in the range of 1 to m-1,
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EP 1 775 838 B9
- store the value of position n+1 of the first look up table (LUT1) in a first storage element,
- store the sum of the value of said first storage element and n in a second storage element,
- if the value in said second storage element is smaller than 2m-1, then store the value in the first look up table
(LUT1) representing the value in said second storage element + 1 in a third storage element, and
- if the value in said first storage element is not equal to the value of said third storage element, then set the
value of position n+1 in the first look up table (LUT1) to the value of said third storage element.
5
10
19. Device according to any one of claims 11 to 18, characterised in, that said device is adapted to scale the input
signal to said D/A converter (A, A’), data-in, to an adapted input signal, data-adapted, by a gain factor, that said
device thus is adapted to;
- offset the binary code of the input signal to 2’s complement conversion if the input signal is not in 2’s complement
representation,
- set said data-adapted to data-in times said gain factor,
- perform the inventive correction calculations,
- 2’s complement convert to offset binary code if the input signal was not in 2’s complement representation, and
- send the data to D/A converter (A, A’).
15
20
25
20. Computer program product, characterised in that said computer program product comprises computer program
code, which, when executed by a computer, will enable said computer to perform a correction of static mismatch
errors in a D/A converter (A, A’) according to any one of claims 1 to 10.
21. Computer program product, characterised in that said computer program product comprises computer program
code, which, when executed by a computer, will enable said computer to act as a device for the correction of static
mismatch errors in a D/A converter (A, A’) according to any one of claims 11 to 19.
22. Computer readable medium, characterised in that said computer readable medium comprises computer program
code according to claim 20 or 21.
30
Patentansprüche
1.
Verfahren für die Korrektur eines statischen Fehlanpassungsfehlers in einem D/A-Umwandler (A, A’), wobei ein
digitales Eingabewort
35
- N Bits umfaßt, wobei das n-te Bit, n=0,1, ..., N-1, des Eingabeworts einen Beitrag zu einem Ausgabestrom
des D/A-Umwandlers (A, A’) steuert, wobei der Beitrag mit einem Gewicht von 2n gewichtet ist, und
- in einen höchstwertigen Teil, ein msb-Wort, und einen niedrigstwertigen Teil, ein lsb-Wort, unterteilt wird und
wobei das msb-Wort durch m msb-Bits dargestellt wird und das lsb-Wort durch l lsb-Bits dargestellt wird, gekennzeichnet durch
- Kalibrieren des D/A-Umwandlers (A, A’) so dass das Gewicht des niedrigstwertigen msb-Bit auf einen Wert
kleiner als 2l gesetzt ist,
- Implementieren einer ersten Nachschlagetabelle (LUT1) in einer ersten Einheit, vor dem D/A-Umwandler (A,
A’) angeordnet, wobei die erste Nachschlagetabelle (LUT1) den höchstwertigen Teil des Fehlers enthält, so
dass ein korrigiertes msb-Wort, c-msb-Wort, gleich dem msb-Wort plus ein Wert ist, der aus der ersten Nachschlagetabelle (LUT1) in Abhängigkeit von dem msb-Wort ausgewählt wird, und
- Implementieren einer zweiten Nachschlagetabelle (LUT2) in der ersten Einheit, wobei die zweite Nachschlagetabelle (LUT2) den niedrigstwertigen Teil des Fehlers enthält, so dass eine erste korrigierte Ausgabe, c1Ausgabe, gleich dem c-msb-Wort plus einem Wert ist, der ausgewählt ist aus der zweiten Nachschlagetabelle
(LUT2) in Abhängigkeit von dem zu dem lsb-Wort addierten c-msb-Wort, wobei ein von der ersten Einheit
ausgegebenes und an den D/A-Umwandler (A, A’) weitergeschicktes digitales Wort die erste korrigierte Ausgabe, c1-Ausgabe, umfasst.
40
45
50
2.
55
Verfahren nach Anspruch 1, dadurch gekennzeichnet, dass, wenn der höchstwertige Teil von c1-Ausgabe von
dem höchstwertigen Teil von c-msb-Wort differiert, dann eine zweite korrigierte Ausgabe, c2-Ausgabe, so eingestellt
wird, dass sie gleich c1-Ausgabe plus dem niedrigstwertigen Bitbereich, 2l, minus der Differenz zwischen den Werten
in zwei benachbarten Positionen in der zweiten Nachschlagetabelle (LUT2) modulo 2l ist.
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EP 1 775 838 B9
3.
Verfahren nach Anspruch 2, dadurch gekennzeichnet, dass, wenn der höchstwertige Teil von c2-Ausgabe von
dem höchstwertigen Teil von c1-Ausgabe differiert, dann eine dritte korrigierte Ausgabe, c3-Ausgabe, so eingestellt
wird, dass sie gleich c2-Ausgabe plus dem niedrigstwertigen Bitbereich, 21, minus der Differenz zwischen den
Werten in zwei benachbarten Positionen in der zweiten Nachschlagetabelle (LUT2) modulo 2l ist.
4.
Verfahren nach Anspruch 2, dadurch gekennzeichnet, dass die Differenz zwischen den Werten in zwei benachbarten Positionen in der zweiten Nachschlagetabelle (LUT2) so eingestellt ist, dass sie die Differenz zwischen dem
Wert in der c-msb-Wort darstellenden Position und dem Wert in der c-msb-Wort +1 darstellenden Position ist.
5.
Verfahren nach Anspruch 3, dadurch gekennzeichnet, dass die Differenz zwischen den Werten in zwei benachbarten Positionen in der zweiten Nachschlagetabelle (LUT2) so eingestellt ist, dass sie die Differenz zwischen dem
Wert in der c-msb-Wort +1 darstellenden Position und dem Wert in der c-msb-Wort +2 darstellenden Position ist.
6.
Verfahren nach einem der vorhergehenden Ansprüche, gekennzeichnet durch das Ableiten der ersten Nachschlagetabelle (LUT1) und der zweiten Nachschlagetabelle (LUT2) durch Einstellen aller Werte in der ersten Nachschlagetabelle (LUT1) und der zweiten Nachschlagetabelle (LUT2) auf null, und dann für jedes n im Bereich von 1 bis
m-1, wobei m der höchste Wert in dem niedrigstwertigen Bitbereich ist;
5
10
15
- Setzen des Fehlers oder der Abweichung eines Ausgabewerts DEVn auf die Differenz zwischen dem erwarteten
Ausgabewert EXPn und einem tatsächlichen Gewicht für einen spezifischen digitalen Eingabewert, ACTn, wobei
der erwartete Ausgabewert EXPn gleich n mal m ist, und das tatsächliche Gewicht ACTn die Differenz zwischen
dem niedrigstwertigen Bitbereich, 2l, und einem analogen Ausgabewert OP(n+1) ist, wobei der analoge Ausgabewert OP(n+1) die analoge Ausgabe ist, die als Reaktion auf einen digitalen Eingabewert IP(n+1) von dem
D/A-Umwandler (A, A’) kommt,
- Setzen des Werts in Position n+1 der ersten Nachschlagetabelle (LUT1) auf die höchstwertigen Bits von DEVn,
und
- Setzen des Werts in Position n+1 der zweiten Nachschlagetabelle (LUT2) auf die niedrigstsignifikanten Bits
von DEVn.
20
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30
7.
Verfahren nach Anspruch 6, gekennzeichnet durch das Erhalten der analogen Ausgabewerte durch Anwenden
einer Rampe von digitalen Eingabewerten IPn am Eingang des D/A-Umwandlers (A, A’) und Messen des analogen
Ausgabewerts, OPn, für jeden digitalen Eingabewert, IPn, für jedes n im Bereich von 1 bis m-1, wobei m der höchste
Wert in dem niedrigstwertigen Bitbereich ist.
35
8.
Verfahren nach Anspruch 7, dadurch gekennzeichnet, dass die analogen Ausgabewerte OPn gemessen und in
Mitteln zur Informationsspeicherung gespeichert werden, wodurch sie für einen späteren Abruf und eine spätere
Verwendung beim Ableiten der ersten Nachschlagetabelle (LUT1) und der zweiten Nachschlagetabelle (LUT2) zur
Verfügung stehen.
40
9.
Verfahren nach Anspruch 6, gekennzeichnet durch Aktualisieren der ersten Nachschlagetabelle (LUT1) ein weiteres Mal für jedes n im Bereich von 1 bis m-1 durch:
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- Speichern des Werts von Position n+1 der ersten Nachschlagetabelle (LUT1) in einem ersten Speicherungselement,
- Speichern der Summe des Werts des ersten Speicherungselements und n in einem zweiten Speicherungselement,
- wenn der Wert in dem zweiten Speicherungselement kleiner als 2m-1 ist, dann Speichern des Werts in der
ersten Nachschlagetabelle (LUT1), den Wert in dem zweiten Speicherungselement +1 darstellend, in einem
dritten Speicherungselement, und
- wenn der Wert in dem ersten Speicherungselement nicht gleich dem Wert des dritten Speicherungselements
ist, dann Setzen des Werts von Position n+1 in der ersten Nachschlagetabelle (LUT1) auf den Wert des dritten
Speicherungselements.
10. Verfahren nach einem der vorhergehenden Ansprüche, gekennzeichnet durch das Skalieren des Eingangssignals
zu dem D/A-Umwandler (A, A’), Daten-Ein, auf ein adaptiertes Eingangssignal, Daten-Adaptiert, um einen Verstärkungsfaktor, durch:
- wenn das Eingangssignal nicht in der 2er-Komplement-Darstellung ist, dann Versetzen des Binärcodes des
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EP 1 775 838 B9
5
10
15
20
Eingangssignals auf eine 2er-Komplement-Konversion,
- Setzen der Daten-Adaptiert auf Daten-Ein mal dem Verstärkungsfaktor,
- Ausführen von Korrekturberechnungen nach einem vorhergehenden Anspruch,
- wenn sich das Eingangssignal nicht in der 2er-Komplement-Darstellung befand, dann 2-er-Komplement-Konversion zum Versetzen des Binärcodes und
- Senden von Daten an den D/A-Umwandler (A, A’).
11. Einrichtung für die Korrektur eines statischen Fehlanpassungsfehlers in einem D/A-Umwandler (A, A’), wobei die
Einrichtung dafür ausgelegt ist, ein digitales Eingabewort, das N Bits umfasst, zu unterteilen, wobei das n-te Bit,
n=0, 1, ..., N-1, des Eingabeworts einen Beitrag zu einer Ausgabe des D/A-Umwandlers (A, A’) steuert, wobei der
Beitrag mit einem Gewicht von 2n gewichtet wird, in einen höchstwertigen Teil, ein msb-Wort, und einen niedrigstwertigen Teil, ein lsb-Wort, wobei das msb-Wort durch m msb-Bits dargestellt wird und das lsb-Wort durch l lsb-Bits
dargestellt wird, dadurch gekennzeichnet, dass die Einrichtung dafür ausgelegt ist, den D/A-Umwandler (A, A’)
zu kalibrieren, so dass das Gewicht des niedrigstwertigen msb-Bit auf einen Wert kleiner als 2l gesetzt ist, dass die
Einrichtung eine erste Nachschlagetabelle (LUT1) und eine zweite Nachschlagetabelle (LUT2) umfasst, dass die
erste Nachschlagetabelle den höchstwertigen Teil des Fehlers enthält, ermöglichend, dass die Einrichtung ein
korrigiertes msb-Wort, c-msb-Wort, erzeugt, das gleich dem msb-Wort plus einem Wert ist, der aus der ersten
Nachschlagetabelle (LUT1) ausgewählt ist in Abhängigkeit von dem msb-Wort, und dass die zweite Nachschlagetabelle den niedrigstwertigen Teil des Fehlers enthält, ermöglichend, dass die Einrichtung eine erste korrigierte
Ausgabe, c1-Ausgabe, erzeugt, die gleich c-msb-Wort plus einem Wert ist, der aus der zweiten Nachschlagetabelle
(LUT2) ausgewählt ist in Abhängigkeit von dem c-msb-Wort addiert zu dem lsb-Wort und wobei die Einrichtung
dafür ausgelegt ist, ein digitales Wort auszugeben und an den D/A-Umwandler (A, A’) weiterzuleiten, wobei das
digitale Wort die erste korrigierte Ausgabe, c1-Ausgabe, umfasst.
25
12. Einrichtung nach Anspruch 11, dadurch gekennzeichnet, dass, wenn der höchstwertige Teil von c1-Ausgabe von
dem höchstwertigen Teil von c-msb-Wort differiert, die Einrichtung dann dafür ausgelegt ist, eine zweite korrigierte
Ausgabe, c2-Ausgabe, gleich c1-Ausgabe plus dem niedrigstwertigen Bitbereich, 2l, minus der Differenz zwischen
den Werten in zwei benachbarten Positionen in der zweiten Nachschlagetabelle (LUT2) modulo 2l zu setzen.
30
13. Einrichtung nach Anspruch 12, dadurch gekennzeichnet, dass, wenn der höchstwertige Teil von c2-Ausgabe von
dem höchstwertigen Teil von c1-Ausgabe differiert, die Einrichtung dann dafür ausgelegt ist, eine dritte korrigierte
Ausgabe, c3-Ausgabe, gleich c1-Ausgabe, gleich c2-Ausgabe plus dem niedrigstwertigen Bitbereich, 2l, minus der
Differenz zwischen den Werten in zwei benachbarten Positionen in der zweiten Nachschlagetabelle (LUT2) modulo
2l zu setzen.
35
14. Einrichtung nach Anspruch 12, dadurch gekennzeichnet, dass die Einrichtung dafür ausgelegt ist, die Differenz
zwischen den Werten in zwei benachbarten Positionen in der zweiten Nachschlagetabelle (LUT2) als die Differenz
zwischen dem Wert in der c-msb-Wort darstellenden Position und dem Wert in der c-msb-Wort +1 darstellenden
Position zu berechnen.
40
15. Einrichtung nach Anspruch 13, dadurch gekennzeichnet, dass die Einrichtung dafür ausgelegt ist, die Differenz
zwischen den Werten in zwei benachbarten Positionen in der zweiten Nachschlagetabelle (LUT2) als die Differenz
zwischen dem Wert in der c-msb-Wort +1 darstellenden Position und dem Wert in der c-msb-Wort +2 darstellenden
Position zu berechnen.
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16. Einrichtung nach einem der Ansprüche 11 bis 15, dadurch gekennzeichnet, dass, für jedes n im Bereich von 1
bis m-1, wobei m der höchste Wert in dem niedrigstwertigen Bitbereich ist, der Wert in Position n+1 der ersten
Nachschlagetabelle (LUT1) die höchstwertigen Bits von DEVn ist, dass der Wert in Position n+1 der zweiten Nachschlagetabelle (LUT2) die niedrigstwertigen Bits von DEVn ist, dass DEVn die Differenz zwischen dem erwarteten
Ausgabewert EXPn und einem tatsächlichen Gewicht für einen spezifischen digitalen Eingabewert ACTn ist, wobei
der erwartete Ausgabewert EXPn gleich n mal m ist, und das tatsächliche Gewicht, ACTn, die Differenz zwischen
dem niedrigstsignifikanten Bitbereich, 2l, und dem analogen Ausgabewert OP(n+1) ist, wobei der analoge Ausgabewert OP(n+1) die von einem spezifischen D/A-Umwandler (A, A’) als eine Antwort auf einen digitalen Eingabewert
IP(n+1) kommende analoge Ausgabe ist, wodurch die Einrichtung eingestellt wird, den statischen Fehlanpassungsfehler von dem spezifischen D/A-Umwandler (A, A’) zu korrigieren.
17. Einrichtung nach Anspruch 16, dadurch gekennzeichnet, dass die Einrichtung Mittel umfasst zur Informationsspeicherung wie etwa chipinterne Fuses, wo die analogen Ausgabewerte OPn gespeichert werden und für das
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Ableiten der ersten Nachschlagetabelle (LUT1) und der zweiten Nachschlagetabelle (LUT2) zur Verfügung stehen.
5
18. Einrichtung nach Anspruch 16, dadurch gekennzeichnet, dass die erste Nachschlagetabelle (LUT1) in der Einrichtung ein weiteres Mal dadurch aktualisiert wird, dass die Einrichtung dafür ausgelegt ist, für jedes n im Bereich
von 1 bis m-1,
- den Wert von Position n+1 der ersten Nachschlagetabelle (LUT1) in einem ersten Speicherungselement zu
speichern,
- die Summe des Werts des ersten Speicherungselements und n in einem zweiten Speicherungselement zu
speichern,
- wenn der Wert in dem zweiten Speicherungselement kleiner als 2m-1 ist, dann den Wert in der ersten Nachschlagetabelle (LUT1), den Wert in dem zweiten Speicherungselement +1 darstellend, in einem dritten Speicherungselement zu speichern, und
- wenn der Wert in dem ersten Speicherungselement nicht gleich dem Wert des dritten Speicherungselements
ist, dann den Wert von Position n+1 in der ersten Nachschlagetabelle (LUT1) auf den Wert des dritten Speicherungselements zu setzen.
10
15
20
19. Einrichtung nach einem der Ansprüche 11 bis 18, dadurch gekennzeichnet, dass die Einrichtung dafür ausgelegt
ist, das Eingangssignal zu dem D/A-Umwandler (A, A’), Daten-Ein, auf ein adaptiertes Eingangssignal, DatenAdaptiert, um einen Verstärkungsfaktor zu skalieren, dass die Einrichtung somit dafür ausgelegt ist:
- den Binärcode des Eingangssignals auf 2er-Komplement-Konversion zu versetzen, wenn sich das Eingangssignal nicht in der 2er-Komplement-Darstellung befindet,
- die Daten-Adaptiert auf Daten-Ein mal dem Verstärkungsfaktor zu setzen,
- die erfindungsgemäßen Korrekturberechnungen durchzuführen,
- 2er-Komplement zu konvertieren, um den Binärcode zu versetzen, wenn sich das Eingangssignal nicht in der
2er-Komplement-Darstellung befand, und
- die Daten an den D/A-Umwandler (A, A’) zu senden.
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20. Computerprogrammprodukt, dadurch gekennzeichnet, dass das Computerprogrammprodukt einen Computerprogrammcode umfasst, der bei Ausführung durch einen Computer ermöglicht, dass der Computer eine Korrektur
von statischen Fehlanpassungsfehlern in einem D/A-Umwandler (A, A’) gemäß einem der Ansprüche 1 bis 10
ausführt.
35
21. Computerprogrammprodukt, dadurch gekennzeichnet, dass das Computerprogrammprodukt einen Computerprogrammcode umfasst, der bei Ausführung durch einen Computer ermöglicht, als eine Einrichtung zu wirken für
die Korrektur von statischen Fehlanpassungsfehlern in einem D/A-Umwandler (A, A’) nach einem der Ansprüche
11 bis 19.
40
22. Computerlesbares Medium, dadurch gekennzeichnet, dass das computerlesbare Medium einen Computerprogrammcode nach Anspruch 20 oder 21 umfasst.
Revendications
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1.
50
55
Procédé de correction d’une erreur de désadaptation statique dans un convertisseur N/A (A, A’), dans lequel un
mot d’entrée numérique
- comprend N bits, dans lequel le n-ième bit, avec n=0,1, ..., N-1, du mot d’entrée commande une contribution
à un courant de sortie du convertisseur N/A (A, A’), la contribution étant pondérée par un poids égal à 2n, et
- est divisé en une partie de poids fort, appelée mot msb, et en une partie de poids faible, appelée mot lsb, et
dans lequel le mot msb est représenté par m bits msb et le mot lsb est représenté par l bits lsb, caractérisé
en ce que :
- on étalonne le convertisseur N/A (A, A’) de façon à ce que le poids du bit msb de poids faible soit réglé
à une valeur inférieure à 2l,
- on met en oeuvre une première table de consultation (LUT1) dans une première unité disposée en amont
du convertisseur N/A (A, A’), la première table de consultation (LUT1) contenant la partie de poids fort de
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l’erreur, afin qu’un mot msb corrigé, ou mot c-msb, soit égal au mot msb plus une valeur qui est choisie
dans la première table de consultation (LUT1) en fonction du mot msb, et
- on met en oeuvre une deuxième table de consultation (LUT2) dans la première unité, la deuxième table
de consultation (LUT2) contenant la partie de poids faible de l’erreur, afin qu’une première sortie corrigée,
appelée sortie-c1, soit égale au mot c-msb plus une valeur qui est choisie dans la deuxième table de
consultation (LUT2) en fonction du mot c-msb additionné au mot lsb, dans lequel un mot numérique fourni
en sortie par la première unité et retransmis au convertisseur N/A (A, A’) comprend la première sortie
corrigée sortie-c1.
5
10
2.
Procédé suivant la revendication 1, caractérisé en ce que si la partie de poids fort de sortie-c1 diffère de la partie
de poids fort du mot c-msb, on fixe une deuxième sortie corrigée appelée sortie-c2 à une valeur égale à sortie-c1
plus la plage de bits de poids faible, 21, moins la différence entre les valeurs contenues dans deux positions
adjacentes dans la deuxième table de consultation (LUT2) modulo 2l.
15
3.
Procédé suivant la revendication 2, caractérisé en ce que si la partie de poids fort de sortie-c2 diffère de la partie
de poids fort de sortie-c1, on fixe alors une troisième sortie corrigée appelée sortie-c3 à une valeur égale à sortieC2 plus la plage de bits de poids faible, 2l, moins la différence entre les valeurs contenues en deux positions
adjacentes dans la deuxième table de consultation (LUT2) modulo 2l.
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4.
Procédé suivant la revendication 2, caractérisé en ce qu’on fixe la différence entre les valeurs contenues en deux
positions adjacentes de la deuxième table de consultation (LUT2) à une valeur égale à la différence entre la valeur
contenue à la position représentant le mot c-msb et la valeur contenue à la position représentant le mot c-msb +1.
5.
Procédé suivant la revendication 3, caractérisé en ce qu’on fixe la différence entre les valeurs contenues en deux
positions adjacentes de la deuxième table de consultation (LUT2) à une valeur égale à la différence entre la valeur
contenue à la position représentant le mot c-msb +1 et la valeur contenue à la position représentant le mot c-msb +2.
6.
Procédé suivant l’une quelconque des revendications précédentes, caractérisé en ce qu’on détermine la première
table de consultation (LUT1) et la deuxième table de consultation (LUT2) en fixant toutes les valeurs contenues
dans la première table de consultation (LUT1) et dans la deuxième table de consultation (LUT2) à zéro puis en ce
que, pour chaque n dans la plage de 1 à m-1, m étant la valeur la plus grnde dans la plage de bits de poids le plus fort ;
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30
- on fixe l’erreur, ou l’écart, d’une valeur de sortie, DEVn, à la différence entre la valeur de sortie à laquelle on
s’attend, EXPn, et un poids réel pour une valeur d’entrée numérique précise, ACTn, la valeur de sortie à laquelle
on s’attend, EXPn, étant égale à n fois m, et le poids réel, ACTn, étant la différence entre la plage de bits de
poids faible, 2l, et une valeur de sortie analogique OP(n+1), la valeur de sortie analogique OP(n+1) étant la
sortie analogique provenant du convertisseur N/A (A, A’) en réponse à une valeur d’entrée numérique IP(n+1),
- on fixe la valeur à la position n+1 de la première table de consultation (LUT1) aux bits de poids le plus fort de
DEVn, et
- on fixe la valeur à la position n+1 de la deuxième table de consultation (LUT2) aux bits de poids faible de DEVn.
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40
7.
Procédé suivant la revendication 6, caractérisé en ce qu’on obtient les valeurs de sortie analogiques en appliquant
une rampe de valeurs d’entrée numériques IPn à l’entrée du convertisseur N/A (A, A’) et en ce qu’on mesure la
valeur de sortie analogique, OPn, pour chaque valeur d’entrée numérique, IPn, pour chaque n dans la plage de 1
à m-1, m étant la valeur la plus grande dans la plage de bits de poids faible.
8.
Procédé suivant la revendication 7, caractérisé en ce que les valeurs de sortie analogiques OPn sont mesurées
et mémorisées dans des moyens de mémorisation d’informations pour ainsi être disponibles en vue d’une extraction
et d’une utilisation ultérieures lorsqu’on détermine la première table de consultation (LUT1) et la deuxième table de
consultation (LUT2).
9.
Procédé suivant la revendication 6, caractérisé en ce qu’on met à jour la première table de consultation (LUT1)
une fois supplémentaire, pour chaque n dans la plage de 1 à m-1, par les opérations suivantes :
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50
55
- on mémorise la valeur de la position n+1 de la première table de consultation (LUT1) dans un premier élément
de mémorisation,
- on mémorise la somme de la valeur du premier élément de mémorisation et de n dans un deuxième élément
de mémorisation,
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5
10
15
20
25
30
- si la valeur contenue dans le deuxième élément de mémorisation est inférieure à 2m-1, on mémorise alors la
valeur contenue dans la première table de consultation (LUT1) représentant la valeur contenue dans le deuxième
élément de mémorisation +1 dans un troisième élément de mémorisation, et
- si la valeur contenue dans le premier élément de mémorisation n’est pas égale à la valeur du troisième élément
de mémorisation, on fixe alors la valeur de la position n+1 contenue dans la première table de consultation
(LUT1) à la valeur du troisième élément de mémorisation.
10. Procédé suivant l’une quelconque des revendications précédentes, caractérisé en ce qu’on adapte l’échelle du
signal d’entrée du convertisseur N/A (A, A’), appelé données-in, à un signal d’entrée adapté, appelé donnéesadaptées, selon un facteur de gain, par les opérations suivantes :
- si le signal d’entrée n’est pas dans une représentation en complément à 2, on décale alors le code binaire du
signal d’entrée pour effectuer une conversion en complément à 2,
- on fixe données-adaptées à données-in fois le facteur de gain,
- on effectue des calculs de correction suivant l’une quelconque des revendications précédentes,
- si le signal d’entrée n’était pas dans une représentation en complément à 2, on effectue alors une conversion
de complément à 2 pour décaler le code binaire, et
- on envoie les données au convertisseur N/A (A, A’).
11. Dispositif destiné à la correction d’une erreur de désadaptation statique dans un convertisseur N/A (A, A’), le dispositif
étant conçu pour diviser un mot d’entrée numérique qui comprend N bits, dans lequel le n-ième bit, avec n=0,1,...,
N-1, du mot d’entrée commande une contribution à une sortie du convertisseur N/A (A, A’), la contribution étant
pondérée par un poids égal à 2n, en une partie de poids fort, appelée mot msb, et en une partie de poids faible,
appelée mot lsb, où le mot msb est représenté par m bits msb et le mot-lsb est représenté par l bits lsb, caractérisé
en ce que le dispositif est conçu pour étalonner le convertisseur N/A (A, A’) de façon à ce que le poids du bit msb
de poids faible soit fixé à une valeur inférieure à 2l, en ce que le dispositif comprend une première table de consultation
(LUT1) et une deuxième table de consultation (LUT2), en ce que la première table de consultation contient la partie
de poids fort de l’erreur, cela permettant au dispositif de produire un mot msb corrigé, appelé mot c-msb, qui est
égal au mot msb plus une valeur qui est choisie dans la première table de consultation (LUT1) en fonction du mot
msb, et en ce que la deuxième table de consultation contient la partie de poids faible de l’erreur, cela permettant
au dispositif de produire une première sortie corrigée, appelée sortie c1, qui est égale au mot c-msb plus une valeur
qui est choisie dans la deuxième table de consultation (LUT2) en fonction du mot c-msb additionné au mot lsb, et
dans lequel le dispositif est conçu pour fournir en sortie et retransmettre un mot numérique au convertisseur N/A
(A, A’), le mot numérique comprenant la première sortie corrigée, sortie c1.
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12. Dispositif suivant la revendication 11, caractérisé en ce que, si la partie de poids fort de sortie c1 diffère de la
partie de poids fort du mot c-msb, le dispositif est alors conçu pour fixer une deuxième sortie corrigée, appelée
sortie c2, à une valeur égale à sortie c1 plus la plage binaire de poids faible, 2l, moins la différence entre les valeurs
contenues en deux positions adjacentes dans la deuxième table de consultation (LUT2) modulo 2l.
40
13. Dispositif suivant la revendication 12, caractérisé en ce que, si la partie de poids fort de sortie c2 diffère de la
partie de poids fort de sortie c1, le dispositif est alors conçu pour fixer une troisième sortie corrigée, appelée sortie
c3, à une valeur égale à sortie c2 plus la plage de bits de poids faible, 2l, moins la différence entre les valeurs
contenues en deux positions adjacentes dans la deuxième table de consultation (LUT2) modulo 2l.
45
14. Dispositif suivant la revendication 12, caractérisé en ce que le dispositif est conçu pour calculer la différence entre
les valeurs contenues en deux positions adjacentes dans la deuxième table de consultation (LUT2) comme étant
la différence entre la valeur contenue à la position représentant le mot c-msb et la valeur contenue à la position
représentant le mot c-msb +1.
50
15. Dispositif suivant la revendication 13, caractérisé en ce que le dispositif est conçu pour calculer la différence entre
les valeurs contenues en deux positions adjacentes dans la deuxième table de consultation (LUT2) comme étant
la différence entre la valeur contenue à la position représentant le mot c-msb +1 et la valeur contenue à la position
représentant le mot c-msb +2.
55
16. Procédé suivant l’une quelconque des revendications 11 à 15, caractérisé en ce que, pour chaque n contenu dans
la plage de 1 à m-1, m étant la valeur la plus élevée de la plage de bits de poids faible, la valeur contenu à la position
n+1 de la première table de consultation (LUT1) est constituée par les bits de poids fort de DEVn, en ce que la
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5
10
15
20
25
30
35
valeur contenue à la position n+1 de la deuxième table de consultation (LUT2) est constituée par les bits de poids
faible de DEVn, en ce que DEVn est la différence entre la valeur de sortie à laquelle on s’attend, EXPn, et un poids
réel pour une valeur d’entrée numérique spécifique, ACTn, la valeur de sortie à laquelle on s’attend, EXPn, étant
égale à n fois m, et le poids réel, ACTn, étant la différence entre la plage de bits de poids faible, 2l, et la valeur de
sortie analogique OP(n+1), la valeur de sortie analogique OP(n+1) étant la sortie analogique provenant d’un convertisseur N/A (A, A’) spécifique en réponse à une valeur d’entrée numérique IP(n+1), le dispositif étant donc réglé
pour corriger l’erreur de désadaptation statique provenant du convertisseur N/A (A, A’) spécifique.
17. Dispositif suivant la revendication 16, caractérisé en ce que le dispositif comprend des moyens destinés à la
mémorisation d’informations, tels que des fusibles intégrés à la puce, dans lesquels les valeurs analogiques de
sortie OPn sont mémorisées et sont disponibles pour la détermination de la première table de consultation (LUT1)
et de la deuxième de consultation (LUT2).
18. Dispositif suivant la revendication 16, caractérisé en ce que la première table de consultation (LUT1) contenue
dans le dispositif est mise à jour une fois supplémentaire par le fait que le dispositif est conçu, pour chaque n dans
la plage de 1 à m-1, pour
- mémoriser la valeur de la position n+1 de la première table de consultation (LUT1) dans un premier élément
de mémorisation,
- mémoriser la somme de la valeur du premier élément de mémorisation et de n dans un deuxième élément
de mémorisation,
- si la valeur contenue dans le deuxième élément de mémorisation est inférieure à 2m-1, mémoriser alors la
valeur contenue dans la première table de consultation (LUT1) représentant la valeur contenue dans le deuxième
élément de mémorisation +1 dans un troisième élément de mémorisation, et
- si la valeur contenue dans le premier élément de mémorisation n’est pas égale à la valeur du troisième élément
de mémorisation, fixer alors la valeur de la position n+1 dans la première table de consultation (LUT1) à la
valeur du troisième élément de mémorisation.
19. Dispositif suivant l’une quelconque des revendications 11 à 18, caractérisé en ce que le dispositif est conçu pour
adapter l’échelle du signal d’entrée du convertisseur N/A (A, A’), appelé données-in, à un signal d’entrée adapté,
appelé données-adaptées, selon un facteur de gain, et en ce que le dispositif est donc conçu pour :
- décaler le code binaire du signal d’entrée pour effectuer une conversion de complément à 2 si le signal d’entrée
n’est pas dans une représentation en complément à 2,
- fixer données-adaptées à données-in fois le facteur de gain,
- effectuer les calculs de correction de l’invention,
- convertir en complément à 2 pour décaler le code binaire si le signal d’entrée n’était pas dans une représentation
en complément à 2, et
- envoyer les données au convertisseur N/A (A, A’).
40
20. Produit à base de programme informatique caractérisé en ce que le produit à base de programme informatique
comprend un code de programme informatique qui, lorsqu’il est exécuté par un ordinateur, permet à l’ordinateur
d’effectuer une correction d’erreurs de désadaptation statiques dans un convertisseur N/A (A, A’) suivant l’une
quelconque des revendications 1 à 10.
45
21. Produit à base de programme informatique caractérisé en ce que le produit à base de programme informatique
comprend un code de programme informatique qui, lorsqu’il est exécuté par un ordinateur, permet à l’ordinateur de
jouer le rôle d’un dispositif destiné à corriger des erreurs de désadaptation statiques dans un convertisseur N/A (A,
A’) suivant l’une quelconque des revendications 11 à 19.
50
22. Support lisible par ordinateur, caractérisé en ce que le support lisible par ordinateur comprend un code de programme informatique suivant la revendication 20 ou 21.
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REFERENCES CITED IN THE DESCRIPTION
This list of references cited by the applicant is for the reader’s convenience only. It does not form part of the European
patent document. Even though great care has been taken in compiling the references, errors or omissions cannot be
excluded and the EPO disclaims all liability in this regard.
Patent documents cited in the description
•
US 4963870 A [0007]
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