Exercise Sheet 1

Transcription

Exercise Sheet 1

Übungen zu Algorithmen und Methoden zur Entwurfsautomatisierung in der Nano- und Mikroelektronik
Prof. Dr. H.-J. Wunderlich/ Dipl.-Inf. G. Bartsch, Dipl.-Inf. T. Bergmann,
SS 2006
Dipl.-Inf. S. Holst, Dipl.-Inf. M. Imhof, Dipl.-Ing. C. Zoellin
ITI
Exercise Sheet 1
1. High-Level Synthesis
The Disydent (http://www-asim.lip6.fr/recherche/disydent/) tools help to go from the
high level description to the actual embedded application implementation verifying the constraints. Among
other tools they contain a high-level synthesis tool chain called UGH (User Guided High-level synthesis)
which will be used to synthesize C-Code into VHDL in this exercise.
In this exercise we want to synthesize this piece of C-Code which implements a GCD (greatest common
divisor) function:
#include <ugh.h>
/*** the communication channels ***/
ugh_inChannel32
work2hcf;
ugh_outChannel16 hcf2work;
/*** registers ***/
uint16 a,b;
uint32 x;
/*** behavior ***/
inline void hcf(void)
{
while (a!=b) {
if (a==b)
break;
else if (a<b)
b = b-a;
else
a = a-b;
}
}
int ugh_main()
{
while (1) {
ugh_read(work2hcf,&x);
a= x&0xffff;
b= (x>>16)&0xffff;
hcf();
ugh_write(hcf2work,&a);
}
}
Note: You can find the source code necessary for this exercise in /cad/tools/amen/hls
The Hcfprocessor.ddp describes this Draft Data Path:
Verification. The ughcgs command verifies if the inputs are coherent and builds the data path by
SS 2006
ITI
concurrent exploration of the behavior and the DDPS.
ughcgs -load Hcfprocessor -C "-I$DISYDENT_DIR/$SYSTEM/include" -save
Hcfprocessor.sl
If the verification is successful, it generates a Hcfprocessor.sl file that contains the data path and a
coarse grain Finite State Machine needed to continue the synthesis. Optimization: The ughbo command
optimizes the CDFG of the description of the Hcfprocessor.sl file.
ughbo -f Hcfprocessor.sl
Making the control unit: The ughfgs command generates the control unit for the clock period given by
the -c switch . In our case, the requested frequency of operation in the specification of the problem is 80
MHz, leading to a 12 ns period. The computed control unit is appended to the Hcfprocessor.sl file.
ughfgs -f Hcfprocessor.sl -ck 12
Obtaining the `VHDL' description of the processor: The ugh2vhdl command builds from the
Hcfprocessor.sl file a `VHDL' description of the entire processor.
ugh2vhdl -all -dir physical -dialect syno -load Hcfprocessor.sl -nr
Exercise: Try to model Bresenham's Algorithm:
int dx := x2-x1
int dy := y2 - y1
int dT := 2*(dy - dx)
int dS := 2*dy
int d
:= 2*dy - dx
point(x, y)
while x < x2 loop
x := x + 1
if d < 0 then
d := d + dS
else
y := y + 1
d := d + dT
end if
point(x, y)
end loop
SS 2006
ITI
2. RT-Level Synthesis
In this exercise we want to synthesize and simulate a simple VHDL Counter example using a testbench.
Note: you find the necessary sources for this exercise in
/cad/tools/amen/counter/
First start the eclipse framework
eclipse
Press OK when it asks you about your default workspace location. Select Workbench on the welcome
screen. Open the Signs perspective by clicking Window->Open Perspective->Other. Select
SignsPerspective and click OK. Create a new Signs project by clicking File->New->Signs Project. Type
counter as project name and select Finish.
To copy the VHDL source files into your newly created project, select File->Import->File system->Next
and navigate to the above mentioned directory. Select both VHDL files and choose Finish.
Examine both VHDL files by double-clicking on them.
To elaborate the test bench, select Net List Viewer and click on the little bee ( “Elaborate... ” ). Open the
hierarchy and select counter->WORK.lib->COUNTER_TB, click OK. Inside the netlist viewer you can
browse into sub-components by double-clicking on them and navigate up using the Up-Arrow in the
toolbar.
To simulate the test bench, choose the Simulator tab, click on the little bee ( “ Simulate... ” ) and select the
counter testbench as described above. Click on the eye-button ( “ Trace... ” ) in the toolbar and shift-select
all testbench signals and click OK. Click the run-button several times to simulate the design.
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3. Exporting a Flat Netlist in ISCAS Format
While still in Eclipse/Signs, go back to the netlist viewer, double click on the counter instance and click on
the little bulldozer ( “ process netlist ” ). Control-Select Constant Propagation and Dissolve, click on OK.
Click on the little floppy disk ( “ Export... ” ) and type in a filename ending with the extension .bench.
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ITI
4. Optimization with SIS
In this exercise we want to use SIS to optimize the synthesized counter from the previous exercise.
First, we have to convert the .bench file from Signs into a .blif file suitable for sis. Print the help and
generate a blif file from your .bench file:
user@rantanplan:~$ perl /cad/tools/amen/counter/iscas2blif.pl -h
now start SIS:
user@rantanplan:~/tmp$ sis
UC Berkeley, SIS 1.3.6 (compiled 2005-06-01 13:14:41)
sis>
You can display the list of other commands in sis using help. Every command has a short usage, which is
printed if you enter the command without options. Now read in the .blif file:
sis> read_blif counter.blif
You will encounter some warning which you can safely ignore.
Now we execute the rugged script provided with SIS, step by step. After every step, you might want to have
a look at the resulting net-list statistics using print_stats and the net-list itself with write_blif -n
sweep; eliminate -1
simplify -m nocomp
eliminate -1
sweep; eliminate 5
simplify -m nocomp
resub -a
fx
resub -a; sweep
eliminate -1; sweep
full_simplify -m nocomp
Write the net-list to a blif-file again:
sis> write_blif -n counter_opt.blif
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ITI
5. Technology mapping
If you look into the just generated counter_opt.blif, you'll notice, that it contains rather complex
operations which are specified using truth-tables. Modeling these using a predefined set of available
primitive gates is called technology mapping. First, the set of available gates and its functions have to be
specified. As a starting point, we copy together the necessary gates from SIS' integrated technology
libraries:
user@rantanplan:~$ cp
/cad/sis/1.3.6/share/sis/sis_lib/mcnc.genlib counter.genlib
user@rantanplan:~$ cat
/cad/sis/1.3.6/share/sis/sis_lib/mcnc_latch.genlib >>counter.genlib
Open the resulting counter.genlib a in an editor and check, which gates are defined in this library. To
perform the mapping using this library, start SIS again and execute the following commands:
read_blif counter_opt.blif
read_library counter.genlib
map
phase -g
write_blif -n counter_mapped.blif
Use print_stats, print_map_stats and print_delay to review the results.
Optional: Using the command line tool blif2vst, you can now create a structural VHDL model of the
mapped net list file:
blif2vst counter.genlib counter_mapped.blif counter_opt.vhdl
To successfully simulate this VHDL, you have to implement the gates used by SIS. To ease this task, you
can remove unnecessary gates from your library and perform the technology mapping again. Modify the test
bench used in task 2 to simulate the optimized counter.
SS 2006
ITI
6. Spice simulation
Now we would like to do analog simulation of the optimized netlist.
perl /cad/tools/amen/counter/blif2spice.pl -i counter_opt.blif -o
counter.sp

Exercise Sheet 1

Transcription

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