Xputer-related Literature: part 2

Xputer-related Literature: part 2
(R. Hartenstein & Co-Authors: Literature on Xputers, MoM, MoPL, PISA and their applications
or, referencing such literature) http://www.fpl.uni-kl.de/xputer-pages/Hartenstein-Xputer-related-Literature_2.pdf
for [1] - [90] see part 1: http://www.fpl.uni-kl.de/xputer-pages/Hartenstein-Xputer-related-Literature.pdf
together with: http://www.fpl.uni-kl.de/staff/hartenstein/par_numbers.pdf
and: http://www.fpl.uni-kl.de/staff/hartenstein/publications.htm
new and old lists
[91] H. Reinig et al.: A Reconfigurable Data-Driven ALU for Xputers; IEEE Workshop on FPGAs for
Custom Computing Machines, FCCM'94, Napa, CA., April 1994. <PDF>
[92] H. Reinig et al.: An FPGA Architecture for Word-Oriented Datapaths; Canadian Workshop on
Field-Programmable Devices, FPD'94, Kingston, Ontario, June 13-16, 1994 <PDF>
[93] H. Reinig, et al.: A Dynamically Reconfigurable Wavefront Array Architecture for
Evaluation of Expressions; Proc. Int'l. Conf. on Application-Specific Array Processors,
ASAP'94, San Francisco, IEEE Computer Society Press, Los Alamitos, CA, Aug. 1994 <PDF>
[94] H. Reinig, et al.: A Reconfigurable Arithmetic Datapath Architecture: GI/ITG-Workshop
"Architekturen für hochintegrierte Schaltungen", Schloß Dagstuhl, Bericht 303, pp. 53-59, Juli 1994 <PDF>
th
[95] H. Reinig, et al.: A New FPGA Architecture for Word-oriented Datapaths; The 4 Int’l
Workshop on Field Programmable Logic and Applications, FPL'94, Prague, Sep 7-10, 1994 <PDF>
[96] A. Ast, J. Becker, et al.: Data-procedural Languages for FPL- based Machines; 4th Int'l
Workshop on Field Programmable Logic and Applications, FPL'94, Prague, Sep 7-10 1994, <pdf>
[97] Xputers and their relations to H/S Codesign; report, Univ. Kaiserslautern, Sep 1994 <PDF>
[98] (f) (fragment): Xputers and their relations to H/S Codesign. Sep 1994, Fachbereich
Informatik, TU Kaiserslautern, Germany (the first of 22 pages History of Xputers) <gif>
[99] K. Schmidt: Parallelizing Compilation for a Novel Data-Parallel Architecture; in: J. P. Gray,
F. Naghdy (eds), PCAT-94, Parallel Computing: Technology and Practice, Wollongong, Australia, Nov. 1994 <pdf>
[100] (invited tutorial) Xputers, a New Computational Paradigm; Institute of Microelectronics;
Singapore, November 1994
[101] K. Schmidt: A Restructuring Compilation Method for the Xputer Paradigm: IWPP 94,
Proc. Int’l Workshop on Parallel Processing, Bangalore, India, Dec. 1994 <PDF>
[102] K. Schmidt: A Restructuring Compilation Method for the Xputer Paradigm: Journal
of the Brasilian Computer Society; Special Issue on Electronic Design Automation, no.2, vo. 2, Nov 1995 <PDF>
[103] K. Schmidt: Combining Structural and Procedural Programming by Parallelizing
Compilation; Proceedings of the Symposium on Applied Computing, Nashville, TN, Feb. 1995
<PDF>
[104] J. Becker, et al.: A Novel Machine Paradigm to Accelerate Scientific Computing;
Computer Science and Informatics Journal, Special Issue of Scientific Computing, Computer Society of India, 1996 <PDF>
[105] (handout and presentation of an invited full day VLSI Design Course) R. Hartenstein
(chair), J. Becker, R. Kress, W. Reinig: Xputers: Principles, Architectures, Performance;
Tutorial on Xputers; LIRMM, University of Montpellier, Montpellier, France, Sept. 1995
[106]. K. Schmidt: A Restructuring Compilation Method for the Xputer Paradigm: Journal of the
Brasilian Computer Society; Special Issue on Electronic Design Automation, no.2, vol. 2, Nov. 1995 <PDF>
[107] J. Becker, et al.: A Novel Two-Level Hardware/Software Co- Design Framework; Journal of
the Brazilian Computer Society, Special Issue on Electronic Design Automation, Dec. 1995 <PDF>
[108] Hardware/Software Co-Design; GI Informatik-Spektrum, 1995
[109] Custom Computing Machines; GI Informatik-Spektrum, 1995 <pdf>
[110] J. Becker, et al.: CoDe-X: A Novel Two-Level Hardware/Software Co-Design Framework;
9th Int’l Conference on VLSI Design, Bangalore, India, Jan. 1996 <PDF> <PDF>
[111] (g) (w. H. Reinig): Novel Sequencer Hardware for High-Speed Signal Processing; Workshop
on Design Methodologies for Microelectronics, DMM'95, Smolenice Castle, Czech Republic, Sept. 1995 <PDF>
[112] H. Reinig, et al.: A Scalable, Parallel, and Reconfigurable Datapath Architecture; 6th
Int'l Symp. on IC Technology, Systems & Applications, ISIC'95, Singapore, Sep 1995 <PDF>
<pdf-2> <pdf-3>
[113] R. Kress: A Datapath Synthesis System for the Reconfigurable Datapath Architecture;
Asia and South Pacific Design Automation Conference, ASP-DAC'95, Makuhari, Chiba, Japan, Aug/Sep 1995 <pdf>
[114] J. Becker, et al.: A Parallelizing Compilation Method for the Map-oriented Machine; Int'l
Conf. on Application-Specific Array Processors, ASAP'95, Strasbourg, France, IEEE CS Pr., July 1995 <PDF>
[115] H. Reinig, et al.: A Reconfigurable Accelerator for 32-bit Arithmetic; Workshop
on Reconfigurable Architectures, Santa Barbara, CA, April 1995 <PDF>
[116] J. Becker, et al.: A Reconfigurable Machine for Applications in Image and Video
Compression; European Symp. on Advanced Networks and Services: Conf. on Compression
Technologies and Standards for Image and Video Compression, Amsterdam, The Netherlands, March 1995 <PDF>
[117] A. Ast, J. Becker, et al.: Data-procedural Languages for FPL- based Machines; Universität Kaiserslautern, Fachbereich Informatik, Interner Bericht, Nr. 264/95, 1995
<PDF>
[118] .J. Becker, R. Kress, H. Reinig: A Novel Hardware/Software Co-Design Framework; J.l of
the Brasilian Computer Society: Special Issue on Electronic Design Automation, no.2, vol. 2, pp.16-26, Nov1995 <PDF>
[119] J. Becker, et al. Two-Level Hardware/Software Partitioning Using CoDe-X; IEEE Int'l
Workshop on Computer Based System Engineering (CBSE'96), Friedrichshafen, Germany, March 1996 <PDF>
[120] J. Becker, et al. Two-level Partitioning of Image Processing Algorithms for the Parallel
Map-oriented Machine; ACM/IEEE International Workshop on Hardware/ Software Co-Design
Codes/CASHE/CODES'96, Pittsburgh, PA, USA, March 18 - 20, 1996 <PDF>
[121] J. Becker, M. Herz, R. Kress, U. Nageldinger: A Partitioning Programming Environment for a Novel
Parallel Architecture; IEEE Int’l Parallel Processing Symp. (IPPS'96), Honolulu, Hawaii, USA, April 1996 <PDF> <pdf2>
[122] J. Becker, M. Herz, et al. A Parallelizing Programming Environment for Embedded Xputerbased Accelerators; High Performance Computing Symp, HPCS'96, Ottawa, Canada, June 1996 <PDF> <pdf2>
[123] R. Kress An Architecture for Highly Parallel Computer Arithmetic; 2nd Int’l Conf. on Highly
Parallel Computing Systems (MPCS'96), Ischia, Italy, May 6 - 9, 1996
[124] J. Becker, et al. Application-specific Microprocessor Design Methodologies: General
Model vs. Tinkertoy Approach; GI / ITG Worksh. on Custom Computing, Dagstuhl, Germany, 19-21 June ‘96 <PDF>
[125] (Invited Tutorial, together w. Jürgen Becker): Xputers and Their Programming
Environment; ARM Advanced RISC Machines, Ltd. Europe, Cambridge, UK, July 24, 1996.
[126] J. Becker, et al.: A Novel Machine Paradigm to Accelerate Scientific Computing;
Computer Sc. and Informatics Journal: Special issue on Scientific Computing, Computer Society of India, 1996 <pdf> <pdf-2>
[127] (N) SYS3: Mapping Systolic Arrays onto Xputers; DRAFT book chapter; July 1996 <PDF>
[128] J. Becker: Hardware/Software Co-Design for data-driven Xputer-based
Accelerators; Proc. 10th International Conference on VLSI Design (Theme: VLSI in Multimedia
Applications), January 4-7, 1997, Hyderabad, India <award> <Xputer Software 1997> <pdf>
[129] J. Becker: A Two-level Co-Design Framework for data- driven Xputer-based
Accelerators; Proc. 30th Hawaii Int’l Con. on System Sciences (HICSS-30), January 7 - 10, 1997,
Wailea, Maui, Hawaii, USA, <Presse-Echo> <inforapid> <freenet> <pdf>
[130] J. Becker, K. Schmidt: Performance Evaluation in Xputer- based Accelerators; Proc. 4th
Reconfigurable Architectures Workshop (RAW-97), in conj. w. 11th Int’l Parallel Processing Symp.,
IPPS'97, Geneva, Switzerland, April 1-5,1997 <PDF>
[131] J. Becker, M. Herz, U. Nageldinger): A Novel Sequencer Hardware for Application
Specific Computing; Proc. 11th Int’l Conf. on Application-specific Systems, Architectures and
Processors, (ASAP`97), Zurich, Switzerland, July 14-16, 1997 <PDF> <pdf2>
[132] R. Kress, U. Nageldinger: An Operating System for Custom Computing Machines based on
the Xputer Paradigm; 7th Int’l Workshop on Field Programmable Logic (FPL`97), London, UK, Sep 1-3, 1997 <PDF>
[133] J. Becker, M. Herz, U. Nageldinger: A Novel Universal Sequencer Hardware; Proc. Fachtagg
Architekturen v. Rechensystemen ARCS'97, Rostock, Germany, Sep 8-11, 1997 <PDF>
[134] J. Becker, M. Herz, U. Nageldinger: Parallelization in Co-Compilation for Configurable
Accelerators; in Proc. Asia and South Pacific Design Automation Conf., ASP-DAC’98, Yokohama,
Japan, February 10 - 13, 1998 <PDF> <pdf2>
[135] (w) Xputer Pages; newsletter, Informatics Dept., TU Kaiserslautern, 1999 <html>
[136] (w) The Xputer Page; newsletter, Informatics Dept., TU Kaiserslautern, 1999 <html>
[137] (w) The Wrong Roadmap Page; newsletter, Informatik, TU Kaiserslautern, 1999 <html>
[138] (w) The Anti-Machine Page; newsletter, Informatik, TU Kaiserslautern, 1999 <html>
[139] The Configware Page; newsletter, Informatik, TU Kaiserslautern, 1999 <html>
[140] The Morphware Page; newsletter, Informatik, TU Kaiserslautern, 1999 <html>
[141] The Flowware Page; newsletter, Informatics Dept., TU Kaiserslautern, 1999 <html>
[142] The Data Streams Page; newsletter, Informatik, TU Kaiserslautern, 1999 <html>
[143] The Kress Array Page; newsletter, Informatik, TU Kaiserslautern, 1999 <html>
[144] The Xputers Page (in German language), newsletter, Informatics Dept., TU Kaiserslautern, 1999 <html>
[145] The auto-sequencing Memory (asM) Page; newsletter, Informatik, TU Kaiserslautern, 1999 <html>
[146] The Generic Address Generator (GAG) Page; newsl., Informatik, TU Kaiserslautern, 1999 <html>
[147] The Reinvent Computing Page; newsletter, Informatik, TU Kaiserslautern, 1999 <html>
[148] M. Herz, Th. Hoffmann, U. Nageldinger, Ch. Schreiber: Interfacing the MoM-PDA to an
Internet-based Development System; 32th Annual Hawaii Int. Conf. on System Science
(HICSS, HICSS-32 ), Jan 1999, Wailea, Maui, Hawaii, USA,1999 <PDF> <the project> <desciption> <crew>
[149] M. Herz, T. Hoffmann, . Nageldinger, Christan Schreiber): XMDS: The Xputer Multimedia
Development System; The 32th Anual Hawaii International Conference on System Science (HICSS,
HICSS-32), Jan 1999, Wailea, Maui, Hawaii, USA, 1999 <PDF> <inforapid> <freenet>
[150] (keynote address): Reconfigurable Computing: Taking off to Overcome the
Microprocessor; PARC Forum, Xerox Palo Alto Research Center, May 13, 1999 <microprogramming-vs-reconfigurable>
[151] R. Kress: rALU Architectures for the Xputer Prototype MoM-3; Nov.1999 <pdf>
[152] M. Herz, Th. Hoffmann, U. Nageldinger: KressArray Xplorer: A New CAD Environment to
Optimize Reconfigurable Datapath Array Architectures; The 5th Asia and South Pacific Design
Automation Conf. ASP-DAC 2000, Pacifico Yokohama, Yokohama, Japan, Jan 25-28, 2000 <PDF> <KXplorer>
[153] (invited presentation) Data-stream-based Computing, Enabling Technology for
Reconfigurable Computing; Seminar Prof. Camargo da Costa, 22 Nov 2002, ENE UnB, Brasilia, Brasil <pdf>
[154] (keynote address); Data-Stream-based Computing and Morphware; Joint 33rd Speedup
and 19th PARS Workshop (Speedup / PARS 2003), Basel, Switzerland, March 2003 <ppt> <pdf>
[155]´ (invited company-internal tutorial presentations): Reconfigurable Computing and its
Enabling Technologies -- for the Personal Supercomputer (PS) to replace the PC;
THALES internal workshop; 18 Sep 2003, Palaiseau, France <award>
[156] Reconfigurable Computing: Paradigmen-Wechsel erschüttern die Fundamente
der Informatik; Prof. Glesner's 60th Birthday Anniv. Colloq; 29 Aug 2003, Darmstadt, Germany <pdf> <pdf-in-english>
[157] N. N.: Xputer Lab's H/S Co-Design Page
[158] (keynote address); Data-Stream-Based Computing: Models and Architectural
Resources; Int’l Conf. on Microelectronics, Devices & Materials (MIDEM 2003), Ptuj, Slovenia, Oct.1-3, 2003 <pdf>
[159] (keynote address) New horizons of very high performance computing (VHPC)
- hurdles and chances; 13th Reconf. Architectures Worksh. (RAW 2006), Rhodos, April 2006, <pdf> <ppt>
[160] (invited paper, invited book chapter): The von Neumann Syndrome (version 1 - very
much different from v. 1); Stamatis Vassiliadis Memorial Symp, Sep 28, 2007, Delft, Netherlands <pdf>
[161] (invited presentation): The Neumann Syndrome calls for a revolution; The 1st Int'l
Works. on High-Performance Reconfigurable Computing Technology and Applications (HPRCTA'07), i.
conj. w. Supercomputing 2007 (SC07), 10.-17. Nov. 2007, Reno, Nevada, USA, <SlideServe> <RG> <acmDL>
[162] (keynote address): The von Neumann Syndrome and the CS Education Dilemma;
The 4th Int'l Worksh on Applied Reconfigurable Computing ( ARC 2008), March 2008, London, UK
[162] (invited presentation) Programmierung jenseits des von- Neumann-Paradigma; 50Jahrfeier des Institut für Technik der Informationsverarbeitung (ITIV), 20. Juni 2008, KIT Karlsruhe, Germany <presentation>
[163] Warum Computer neu erfunden werden müssen; 2010 <pdf>
[164] (invited presentation): How many Dimensions has the Space beyond
Reconfigurable Computing? HiPEAC Computer Systems Week, May 12 -16, 2014, Barcelona, Spain <pdf2>
[165]
also see Reiner's publications:
http://www.fpl.uni-kl.de/staff/hartenstein/publications.htm
[166] J. Becker, R. Hartenstein: Real-time Prototyping in Microprocessor/Accelerator
Symbiosys; Proc. 9th Int’l Workshop on Rapid System Prototyping, 1998 (RSP98). 3-5 June 1998, Leuven <IEEE>
[167] Reiner Hartenstein: invited paper: The Microprocessor is no more General Purpose:
why Future Reconfigurable Platforms will win; International Conf. on Innovative Systems in
Silicon (ISIS 1997), Austin TX, USA, Oct 8-10, 1997 <pdf> <pdf2>
[168] A. Radunovic, V. Milutinovic: A Survey of Reconfigurable Computing Architectures;
FPL'98 From FPGAs to Computing Paradigm - 8th International Workshop FPL'98, Tallinn, Estonia,
August 31 - September 3, 1998"; LNCS No. 1482, Springer-Verlag Berlin/Heidelberg, 1998 - ISBN 3540-64948-4 The leading international conference series on Field-Programmable Logic (FPL) <Spr>
[169] R. Hartenstein, T. Hoffmann, U. Nageldinger: (embedded tutorial): A Decade of Research on
Reconfigurable Architectures - a Visionary Retrospective; Int'l Conf. on Design Automation and Testing in Europe 2001 (DATE’01), Exhibit & Congress Center, Munich, March 2001 <pdf> <pdf2>
[170] R. Hartenstein, M. Herz, F. Gilbert: Designing for Xilinx XC6200 FPGAs; The 8th
International Workshop on Field-Programmable Logic and Applications (FPL’98), Tallinn, Estonia, Aug
31- Sep 3, 1998. Proc. editors: R. Hartenstein, A. Keevallik, Springer-Verlag, Germany, 1998 <pdf>
[171] R. Hartenstein, M. Herz, Th. Hoffmann, U. Nageldinger: Exploiting Contemporary
Techniques in Reconfigurable Accelerators; Proc. 8th Int’l Workshop on Field-Programmable
Logic and Applications (FPL’98) , Tallinn, Estonia, Aug 31- Sep 3, 1998. Proc.: Reiner W. Hartenstein,
Andres Keevallik, Lecture Notes in Computer Science 1482, Springer-Verlag, 1998 <pdf>
[172] J. Becker, R. Hartenstein: Automatic Parallelism Exploitation for FPL-Based
Accelerators; Proc. 31st Hawaii International Conference on Systems Sciences (HICSS, HICSS31), January 1998, Kohala Coast, Big Island, Hawaii, USA <Xplore>
[173] An Innovative Methodology for High-Level Language Programmable Reconfigurable Computing Machines; 112 References N. N. wo ???? 1998--- nicht in Publ Liste
[174] W. Mangione-Smith, B. Hutchings, D. Andrews, A. DeHon, C. Ebeling, R. Hartenstein, O. Mencer,
J. Morris, K. Palem, V. Prasanna, H. Spaanenburg: Seeking Solutions in Configurable
Computing; IEEE Computer, 30/12, December 1997 <pdf> <pdf2>
[175] W. Mangione-Smith, B. Hutchings, D. Andrews, A. DeHon, C. Ebeling, R. Hartenstein, O. Mencer,
J. Morris, K. Palem, V. Prasanna, H. Spaanenburg: Current Issues in Configurable
Computing Research
[176] R. Hartenstein, A. Hirschbiel, K. Schmidt, M. Weber: A Novel Paradigm of Parallel
Computation and its Use to Implement Simple High-Performance Hardware, inside
Future Generation Computer Systems 7 91/92, North Holland: Invited reprint of InfoJapan'90, Tokyo,
Japan, 1990 <pdf>
[177] J. Becker, R. Hartenstein, M. Herz, U. Nageldinger): A General Approach in System
Design Integrating Reconfigurable Accelerators; Proceedings of the IEEE 1966 Int’l Conf.
on Innovative Systems in Silicon (ISIS); Austin, TX, USA, Oct 1996 <pdf>
[178] J. Becker, R. Hartenstein, M. Herz, U. Nageldinger: An Embedded Accelerator for Real World
Computing; IFIP Int'l Conf. on Very Large Scale Integration, VLSI`97, Gramado, Brazil, Aug 26-29, 1997 <pdf> <pdf2>
[179] J. Becker, R. Hartenstein: A Two-level Co-Design Framework for data-driven
Xputer-based Accelerators; Proceedings 30th Hawaii International Conference on System
Sciences (HICSS-30), Jan 7-10, 1997, Wailea, Maui, Hawaii, USA, <pdf>
[180] J. Becker, R. Hartenstein, M. Herz, U. Nageldinger: Outline of a Methodology for Coarse
Grain Reconfigurable Computing Machines;
wo ???
wann ??? [181] R. Hartenstein, R. Kress: rDPA: An Architecture for Highly Parallel Computer
Arithmetic; Instituto di Ricerca sui Sistemi Informatici Paralleli (I.R.S.I.P.), v. Pietro Castellino 111
80131 NAPOLI NA Conference Proceedings | 1996 RDPA 2009 Announcement - GetInfo
https://getinfo.de/app/RDPA-2009.../id/BLSE%3ARN246595743
[182] J. Becker et al.: An Embedded Accelerator for Real Time Image Processing; 8th
EUROMICRO Workshop on Real Time Systems, L'Aquila, Italy, June 1996 <pdf>
[183] (b) (w. J. Becker, M. Herz, et al.): Co-Design and High Performance Computing:
Scenes and Crisis; Proc. Reconfigurable Technology for Rapid Product Development & Computing - Part of SPIE's
Int'l Symposium VOICE, VIDEO and DATA COMMUNICATIONS, PHOTONICS EAST, Boston, USA, Nov 1996 <pdf>
[184] J. Becker, et al.: High-Performance Computing Using a Reconfiigurable
Accelerator; CPE Journal, Special Issue of Concurrency Practice and Experience, John Wiley & Sons Ltd.,1995 <pdf>
[185] [89] A. Ast, J. Becker, R. Hartenstein, H. Reinig, K. Schmidt, M. Weber (invited paper): Xputer: ASIC or
Standard Circuit ?; GME-Fachtagung Dresden, 1993 <pdf>
[186] H. Reinig, K. Schmidt: Vorschläge zur MOPL-Syntax; report, Informatik, TU Kaiserslautern, 19. 11. 1990
[187] {58] R. Hartenstein, A. Hirschbiel, M. Riedmüller, K. Schmidt, M. Weber: A Novel ASIC Design Approach
Based on a New Machine Paradigm; IEEE Journal of Solid State Circuits, July 1991 <pdf> <pdf>
[188] An Emerging Technology; (paper download page); http://xputers.informatik.uni-kl.de/papers/main.html
[189] references of [190] "Xputer related to Hardware/Software Co-Design"; <html>
[190] Xputer related to Hardware/Software Co-Design; http://www.fpl.uni-kl.de/xputer/intro.html
[191] Xputer Publication List; http://www.fpl.uni-kl.de/xputer/xputer_abstracts.html
[192] About Xputers; http://www.fpl.uni-kl.de/xputer/about_xputers.html
[192] Xputer-related Literature (Part 1); http://xputer.de/Hartenstein-Xputer-related-Literature.pdf
[193] Xputer-related Literature: Part 2; http://xputer.de/Hartenstein-Xputer-related-Literature_2.pdf
[194] Xputer related Publications, Reports etc. ###### scannen !!!! ####
[195] M. Vorbach, J. Becker: Reconfigurable Processor Architectures for Mobile Phones; Proc.
IPDPS - IEEE Int'l Parallel and Distributed Processing Symposium, 22-26 April 2003, Nice, France <pdf>
[196] R. Hartenstein (keynote): Are we Really Ready for the Breakthrough ? [Morphware]; 10th
Reconfigurable Architectures Workshop 2003 (RAW 2003) - IPDPS - IEEE Int'l Parallel and Distributed Processing
Symposium, 22-26 April 2003, http://www.fpl.uni-kl.de/staff/hartenstein/lot/HartensteinRAW2003.pdf
[197] J. Becker, R. Hartenstein (invited paper): Configware and Morphware going Mainstream;
Journal of Systems Architecture 49 (2003) 127–142; http://www.sciencedirect.com/science/article/pii/S1383762103000730 http://www2.fiit.stuba.sk/~flochova/-Configware%20and%20morphware%20going%20mainstream.pdf http://www.fpl.uni-kl.de/staff/hartenstein/lot/Juergen-J-Syst-Arch-2003.pdf
[198] R. Hartenstein (invited paper): Trends in Reconfigurable Logic and Reconfigurable
Computing; 9th Int’l Conf. on Electronics, Circuits and Systems (ICECS 2002), Dubrovnik, Croatia, 2002. (Vol:2 ) <pdf>
[199] (invited paper) Michael Herz, Miguel Miranda, Erik Brockmeyer, Francky Catthoor: Memory Addressing
Organisation for Stream-based Reconfigurable Computing; 9th IEEE International Conference
on Electronics, Circuits and Systems - ICECS 2002, September 15-18, 2002, Dubrovnik, Croatia. <pdf>
[200] R. Hartenstein: A Roadmap to New Horizons in High Performance Computing 2003 <pdf>
[201] R. Hartenstein (keynote address): Stream-based Computing - Antimatter of Informatics; The
1st Int'l Conf. on Intelligent Computing and Information Systems (ICICIS 2002), Cairo, Egypt, June 24-26, 2002. <pdf>
[202] R. Hartenstein, A. Hirschbiel, M.Weber: Non-von-Neumann: Is the Technology Transfer an
Achievable Goal ? submitted to ITG/GI-Konferenz Architektur von Rechensystemen, March 1990, Munich, Germany
[203] R. Hartenstein (keynote):The Digital Divide of Computing IPDPS’04, Santa Fe, US, <pdf> <pdf2> <ppt>
[204] R. Hartenstein (invited presentation) European Research Projects on CAD for VLSI; Fujitsu Corporation, Research
Laboratories, Kawasaki, Japan, September 1985
[205] Klaus Schlüter: Xputer - Innovationen für den Multimedia-Markt; Funkschau 5/1992
[206] R. Hartenstein. A. Hirschbiel, M.Weber: Rekonfigurierbare ALU erlaubt Parallelisierung auf
unterster Ebene; VMEbus, 1990 <pdf>
[207] N. N.: FQA about Xputers; CSG, TU Kaiserslautern
[208] R. Hartenstein, J. Becker, R. Kress: Custom Computing Machines vs. Hardware/Software
Co-Design: from a globalized Point of View; FPL'96, Darmstadt, September 1996
[209] A. Ast, H. Reinig, M. Riedmüller, K. Schmidt: Übersicht über Hard- und Soft-warearbeiten für
die MoM3; Bericht, Fachbereich Informatik, TU Kaiserslautern, 18. Januar 1991 <pdf>
[210] Karin Schmidt: Xputer - eine Alternative zum Computer ? Innovatives Hochleistungs-
Rechnerprinzip aus Kaiserslautern; Informatik, UNI SPECTRUM 3 - UNIVERSTIÄT KAISERSLAUTERN, Juli 1990
[211] R. Hartenstein (invited presentation): Data-Stream-based Computing: Antimaterie der KernInformatik; 60 Semester Informatik I, Festkolloquium der Universität Dortmund, 18. - 19. Juli 2002 <pdf>
[212] N. N.: Integrated Circuits having been manufactured for the Kaiserslautern part
of the E.I.S. Project; <pdf>
[213] R. Hartenstein: How to Cope with the Power Wall; 25th PATMOS workshop, Salvador,
Bahia, Brasil, <pdf> (click into the red field)
[214] Lexicon Freenet: Xputer; <html>
[215] Wikipedia_de: Xputer; <pdf>
[216] Wikipedia_en: Xputer; <pdf>
[217] R. Hartenstein: Morphware and Configware; Chapter in: Albert Zomaya: Handbook of
Nature-Inspired and Innovative Computing; Springer-Verlag, December 2009 <Spr>
[218] R. Hartenstein (only submitted): THE VON NEUMANN SYNDROME (version no. 2 –
very much different from version no. 1); SAMOS VI, Samos, Greece, July 2006 <pdf> <pdf2>
[219] A. Ast, H. Reinig, K. Schmidt, M. Weber: A General Purpose Xputer Architecture
derived from DSP and Image Processing; in M. A. Bayoumi (ed.): VLSI Design Methodologies
for Digital Signal Processing Architectures, Kluwer Academic Publishers, p. 365-394, 1994 <Spr>
[220] Dale Meinks, Andreas Pietsch: Xputer; weblearning: Vorlesungs-Skript, (mirror), Wintersemester 1999, Universität Bremen
[221] N. N.: Geschichte der Prozessoren - Die Idee der Xputer - Ein Xputer Konzept Das Xputer Prinzip; (Zusammenfassung), Universität Bremen, 1999
[222] Reiner Hartenstein on SlideServer <SlideServ>
[223] Reiner Hartenstein (conference opening keynote): Reconfigurable Computing and the
von Neumann Syndrome; The 7th International Conference on Algorithms and Architectures for
Parallel Processing (ICA3PP ), Hangzhou, China, June 11-14, 2007 <SlideServ> <pdf> <pdf2>
[224] Reiner Hartenstein (keynote address): Stonewalled Progress inComputing Efficiency;
Chip in Brasilia, SBCCI 2012, The 25th Symposium on Integrated Circuits and Systems Design; August
30 - September 2, 2012, Brasilia, DF, Brasil,
<SlideServ> <pdf> <pdf2>
[225] Reiner Hartenstein: CS Curricula Update – proposed: by Adding Reconfigurable
Computing; EAB board of directors meeting, IEEE Computer Society, November 1, 2003,
Philadelphia, PA, USA <SlideServ> <pdf>
[226] (Reiner Hartenstein:) list of 15 different presentations; <SlideServ>