Cliquez pour modifier le style du titre

Transcription

Thermal Modeling Methodology
for Fast and Accurate System-Level
Analysis: Application to a
Memory-on-Logic 3D Circuit
Cristiano Santos1,2, Pascal Vivet1,
Philippe Garrault3, Nicolas Peltier3, Sylvian Kaiser3
1CEA-LETI,
FR
2UFRGS, BR
3DOCEA Power, FR
www.cea.fr
&
Thermal
issues
in
modern
SoCs
Increasing thermal issues
Technology scaling = ↑higher power density
3D stacking with TSVs = ↑↑even higher power density
and ↓reduced heat dissipation properties
 Higher lateral thermal resistance due to thinned wafers
 Poor conductive materials used to bond stacked dies
Temperature impacts
Power consumption
Peak performance
Ageing
Package costs
How to perform thermal modeling to enable early
exploration of thermal issues including 3D?
&
© CEA. All rights reserved
P. Vivet | DAC’14 User Track | 2-5 June 14
|2
Thermal
Analysis:
state
of
the
art
Low-level tools:
Multiphysics simulation : FloTherm (Mentor Graphics), Icepack (ANSYS), Marc (MSC) , COMSOL
 General-purpose FEM solutions with no specific support for IC design flows
Post-layout level : HeatWave (Gradient DA), Apache (ANSYS)
 Adapted for short term analysis at die level but long simulation times for multiple power scenarios
Those solutions are time consuming methods thus not suitable for system-level simulations
High-level tools:
Architectural and system-level thermal simulators must support:
 Fast transient thermal analysis to be used in power-thermal coupled simulations
 Different granularity scales: from large structures (package, interposer and board) to very fine-grain
elements (TSVs, C4-bumps and copper pillars) with both high impact on model accuracy
Existing solutions:
 Mostly academic tools like HotSpot (Virginia) and 3D-ICE (EPFL)
 No support for fine-grain structures with heterogeneous distribution
No solution for fast transient thermal simulation of complex systems with unrestricted support for fine
grain structures required for 3D integration, flip-chip designs or BGA-like packaged circuits
&
|3
Outline
Cliquez pour modifier le style du
titre
Introduction
State of the Art
Thermal Modeling Methodology using ATM
WIOMING : a Memory-on-Logic 3D Circuit
Correlation of Thermal model wrt Silicon Measurements
System Level Exploration of Thermal Impact of 3D
Conclusion
&
|4
Thermal
Modeling
Methodology
Thermal modeling based on DOCEA™ ATM tool:
Based on a numerical finite difference method
Heat transfer modeled via full 3D heat diffusion in solid
materials with no restriction to heat flow paths
Highly compacted thermal model (CTM) with good
tradeoff between accuracy and efficiency
API + GUI for easy model creation/updates
CTM generation fully automated by Python scripts
 Four main contributions:
Automation of thermal model construction by parsing Design Floorplan (LEF/DEF format)
Automated homogenization methodology to reduce complexity while preserving accuracy
Validation of proposed approach on a Memory-on-Logic 3D circuit
System Level Exploration of 3D Thermal effects
&
|5
Thermal
Model
:
input
data
LEF/DEF parser implemented within ATM
Die size and placement of power sources, TSVs, u-bumps and
C4-bumps can be read into ATM from initial explorative
floorplans or final layout databases
Input data organized as follows:
Material thermal property library: CSV file
Circuit description: parsed from floorplan (LEF/DEF format)
and saved as CSV files
Technology settings: thickness, diameter and material used
for every structure of a specific technology
CSV format is widely used for system-level
exploration
Allow fast iteration and manual modifications
&
|6
Thermal
Model:
Material
Homogenization
Material Homogenization:
This technique consists in calculating the equivalent
anisotropic material properties for a heterogeneous
layer containing multiple structures
A set of geometries are identified to go through
material homogenization
Once the equivalent material is calculated, those
original geometries are then replaced by simplified
structures
Package solder balls
Array of TSVs and u-bumps
Material homogenization applied to :
Layer stacking structures + Array areas
Objective is to reduce the number of geometries
going for extraction while keeping the spatial accuracy
Fully Automated using Python API
&
|7
WIOMING,
a
Memory-on-Logic
3D
Circuit
WIOMING circuit floorplan
D. Dutoit, et al. "A 0.9 pJ/bit, 12.8 GByte/s WideIO Memory Interface in
a 3D-IC NoC-based MPSoC“, VLSI-Symposium, 2013.


WIOMING circuit
 Many-core architecture, STMicroelectronics 65nm
 TSV middle (diam 10µm), µ-bumps (diam 20um)
 3D Assembly : Die2Wafer, Face2Back, FlipChip
Stacking a WideIO compatible DRAM
&


WIOMING circuit instrumented with
 8 Heaters [Can generate each 1Watt]
 7 Thermal Sensors [Accuracy ~1°C after calibration]
Full Thermal Software Control on chip & board
to perform accurate 3D Thermal Characterization
|8
WIOMING
ATM
model:
from
board
to
chip
level
 +6K circuit structures
 Board-level including PCB,
socket and package
 Chip-level with stacked
dies, TSVs and u-bumps




&
27 power sources
26 areas for heat exchange
Multi-corner CTM generation
+2k lines of Python script
|9
Model Compaction Results & Tool Performance Results
Material Homogenization & Model Reduction Results
130x less geometries after material homogenization
60x less nodes after material homogenization
570x less nodes after model reduction
# geometries
# defined materials
# extracted nodes
System physical representation
Before
After
After
homogenization
homogenization
reduction
+6k
71
-23
44
-18 million
231k
405
ATM Tool Performances
a
Per simulation time step
Highly compacted thermal model for static and dynamic thermal analysis
Very fast transient simulations compatible with system-level exploration
&
| 10
WIOMING
:
Thermal
Correlation
Simulation vs. Silicon comparison for various profiles :
 Steady-state analysis:


Very good accuracy of hot spot evaluation (avg=3.96% and worst=13.41%)
CTM is able to capture the spatial temperature distribution
 Transient response (staircase stimuli)



Temp. vs Power for various hot spot distances
High thermal time constant due to package socket and board
Good fitting between simulation and measurement data plots
Thermal time constant error in the 5% – 40% range
 Transient response (PWM shape)


Good fitting between simulation and measurement data
CTM able to model the multiple thermal time constants of the system
Transient step response
PWM response for various PWM periods
&
| 11
Accuracy
Impact
of
Material
Homogenization
 Steady-State analysis experiments with:





1) No homogenization procedures (all fine-grain structures are ignored)
2) Homogenization without selecting localized areas (flat)
Full homogenization approach (reference)
Case 1 -> average error = 51% | worst case error = 81%
Case 2 -> average error = 7% | worst case error = 14%
Properly selecting regions to apply material homogenization brings
considerable accuracy to the spatial temperature distribution
No Homogenization
&
Flat Homogenization
| 12
Impactpour
of board
components
Cliquez
modifier
le styleon
dusilicon
titre

Not accounting for the components mounted on the board introduces an additional
average error of 24% in the steady-state temperature. Worst case error is 43.66%.

Those results show that :
 Poor power modeling of the board elements will have strong accuracy impact !
 Thermal modeling approach being focused either only on board-package or silicon
level is not enough for accurate thermal analysis.
Error when removing PCB components
&
| 13
Exploration
Thermal
Impactle
ofstyle
Die Thickness
Cliquezofpour
modifier
du titre
Compared 3D die version with 2D die versions
For various 2D die thickness (200/300/500µm)
For same hotspot power budget (4 Watt HotSpot in die bottom left)
?
3D die temperature
increase versus
2D die versions
(wrt hotspot distance)
 Very strong effect of die thickness :
o Thin 2D die has worse behavior than 3D die
o Thick 2D die provides better dissipation
&
Industry is driven by reduced form factors
Beware of thermal effects !
| 14
Exploration
ofmodifier
Thermal le
Impact
of TSVs
Cliquez pour
style du
titre
 TSV Thermal Properties :

TSV Ø10µm, pitch 40µm, SiO2 isolation layer 0.25µm

Thermal Conductivity of a TSV array (Homogenized material)
Thermal
Conductivity
Thermal Impact of TSV
Kxy = 133
increased horizontal resistance
negative impact for hotspots
Kz = 159
reduced vertical resistance
good for average power
* Thermal Conductivity of silicon only : 150 W/mK
 Exploration of WIOMING Circuit Testcase :
 Comparing with TSVs vs. without TSVs
Power
dissipation
Hotspot – a)
Hotspot – b)
Uniform
Temperature
difference
+ 2.22%
+ 5.89%
- 0.02%
 TSV does not reduce temperature for uniform power

Due to very low TSV density (3%)
 But may lead to temperature increase for hotspot

&
Must take care of TSV  Hotspot placement !!!
| 15
Conclusion
Thermal Model in ATM tool can be fully automated
DOCEA™ ATM tool providing an API for Python scripting
Die Floorplan parsed from LEF/DEF database
Material homogenization, to reduce model complexity, maintain accuracy
Thermal correlation with a Memory-on-Logic 65nm 3D circuit
Steady State analysis : less than 4% error, accurate evaluation of Hotspots
Transient step response : 5% – 40% error in thermal response time
System-level thermal model: accuracy versus simulation time
Must focus on all levels: from board & package to die fine grain structures
Efficient compaction engine allowing fast thermal simulation and system-level exploration
System Level Exploration Examples :
 Die thickness impact on temperature : 2D very thin die can be worse than 3D die
 TSV impact on temperature : care must be taken for Hotspot & TSV placement
Next steps
Parameter sensitivity analysis for enhanced early thermal exploration
Support for 3D stacking configuration files and std package formats
&
| 16

Cliquez pour modifier le style du titre

Transcription

Documents pareils

Keratherm - Thermal Grease KP 12 silicone free

Keratherm - Thermal Grease KP 92, KP 97, KP 12

info - ITF Technologies Inc.

HVAC CETAB engineering presentation

SEMCO Engineering- Qualiflow Therm Jipelec ADDRESS: 395, rue

thermal histories

PULSE Systems, Inc

arctic mx-2 - Newegg.com

Set List Fontoy 2014-1

REPERTOIRE ROCKFELLER septembre 2016 contact

ISB Online Store is OPEN! La Boutique du LIB est maintenant en

AUSTRIAN MASTERPLAN-THERMAL ENERGY STORAGE

Homogenization Modeling and Parametric Study of Moisture

Quad, Serial Input, 12-Bit, Voltage Output Digital-To