Zynq™ All Programmable SoC : Embedded Systems

Course Outline - Ref:004902A - 02/20/2017
Zynq™ All Programmable SoC : Embedded Systems Hardware Design
2 days
OBJECTIVES
This course brings experienced FPGA designers up to speed
on developing embedded systems using the Vivado™ IP
Integrator (IPI).
The features and capabilities of the Zynq AP as well as
concepts, tools, and techniques are included in the
lectures and labs.
The hands-on labs provide students with experience
PREREQUISITES
FPGA design and Vivado™ Design Suite experience
Zynq™ All Programmable SoC : system architecture training
designing, expanding, and modifying an embedded
(004901A) or equivalent knowledge
system, including adding and simulating a custom AXI-
Basic understanding of microprocesseur and FPGA
based peripheral.
architecture
Basic understanding of C programming
Basic HDL modeling experience
RELATED TRAININGS
CONFIGURATIONS
Zynq™ All Programmable SoC : System Architecture
Zynq™ All Programmable SoC : Embedded Systems Advanced
Software Configuration :
Hardware Design
Xilinx Vivado™ Logic Edition 2015.1
Zynq™ All Programmable SoC : Embedded Systems Software
Hardware configuration:
Recent computer (i5 or i7)
Design
Windows 7 64b
C language for real-time and embedded applications
At least 8GB RAM
Minimum display resolution 1024 x 768,
recommended 1920x1080
PARTNERS
On Site training : video projector
Tool
CHAPTERS
Software Development Using SDK
Lab : Adding and Downloading Software
1ST DAY
Introduction to AXI
Embedded Design Overview
Interrupts
Vivado™ IP Integrator and the Processing System Configuration
Adding Hardware to an Embedded Design
Wizard
Lab : Adding IP to a Hardware Design
Lab : Hardware Construction using the Vivado™ IP Integrator
2ND DAY
MVD Training - 106 avenue des guis - 31830 Plaisance du Touch - France
Ph : +33 (0) 5 62 13 52 32 - Fax : +33 (0) 5 61 06 72 60 - www.mvd-fpga.com
SIRET : 510 766 066 00029 - Tax Id : FR 74510766066 - NAF : 8559A
Training center registration: 73 3105366 31
1
Course Outline - Ref:004902A - 02/20/2017
Lab : Building custom AXI IP
Cortex-A9 Processor Basics
Designing a custom AXI peripheral
Bus Functional Model Simulation
Using the Create and Package IP Wizard to build a custom AXI
Lab : BFM simulation of custom AXI IP
Adding Custom IP to the Embedded System
Peripheral
Lab : Integrating a custom peripheral
NOTES
Training manuals will be given to attendees during training in print.
CONTACT
Tel : 05 62 13 52 32
Fax : 05 61 06 72 60
[email protected]
MVD Training - 106 avenue des guis - 31830 Plaisance du Touch - France
Ph : +33 (0) 5 62 13 52 32 - Fax : +33 (0) 5 61 06 72 60 - www.mvd-fpga.com
SIRET : 510 766 066 00029 - Tax Id : FR 74510766066 - NAF : 8559A
Training center registration: 73 3105366 31
2