Proposition de Stage Laboratoire - Ief - Université Paris-Sud
Transcription
Proposition de Stage Laboratoire - Ief - Université Paris-Sud
Proposition de Stage Laboratoire: Institut d’Electronique Fondamentale (IEF) Adresse: Département Nanoélectronique, Bât 220, Université Paris-Sud, 91405 Orsay Directeur du laboratoire: A. De Lustrac Responsable(s) du stage: Joseph FRIEDMAN & Damien QUERLIOZ Site web: http://www.ief.u-psud.fr/~friedman/projects.html, http://www.ief.u-psud.fr/~querlioz/ E-mail: [email protected], [email protected] Téléphone: 01.69.15.43.40, 01.69.15.33.58 Spintronic Logic Design Automation for Unconventional Beyond-CMOS Computing Why? The very large scale of modern computing systems necessitates the use of algorithms that design hardware that performs complex logical functions. These logic synthesis algorithms decompose a complex logic function into its basis Boolean elements. Spintronics – the utilization of electron spin in addition to charge – is a revolutionary new path for computing. However, spintronic logic gates perform unconventional Boolean functions, providing basis logic gate sets inconsistent with CMOS logic design algorithms. To efficiently construct large-scale spintronic integrated circuits, it is necessary to create logic design algorithms tailored specifically to spintronic computing. What? Develop algorithm that automatically designs spintronic logic circuits. How? 1) Study CMOS design algorithms and spintronic logic gates. 2) Develop algorithm for constructing complex logic circuits based on a spintronic basis logic gate sets. 3) Create computer program that implements design algorithm for particular spintronic basis logic gate set. 4) Publish paper(s) describing logic design algorithm and providing comparisons to CMOS. For students focused on: Electrical Engineering, Computer Science, or Computer Engineering. The internship should be 10 weeks minimum.