Intel® 845 Chipset Family and 845G Chipset Family

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Intel® 845 Chipset Family and
845G Chipset Family Platform
Interoperability
Technical White paper
October 2002
Revision 1.3
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Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel® 845, 845E, 845G, 845GL, 845GE, 845PE, 845GV chipsets may contain design defects or errors known as errata which may cause the
product to deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Intel, Pentium and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other
countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2002, Intel Corporation
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Table of Contents
1
Overview ............................................................................................................................. 5
2
Technical Background......................................................................................................... 6
3
Summary............................................................................................................................. 7
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Revision History
Rev. No.
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Description
Rev. Date
1.2
Initial Release
August 2002
1.3
Added references to 845GE, 845PE, 845GV chipsets
October 2002
Overview
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1
Overview
The Intel 845 Chipset Family, which consists of the Intel® 845 and 845E chipsets, and 845G
Chipset Family, which consists of the Intel® 845G, 845GL, 845GV, 845GE, and 845PE chipsets,
provide efficient, high bandwidth communication channels connecting the processor, the memory,
the I/O subsystem, and other components together to deliver a stable mainstream desktop platform
solution.
The chipsets support a wide range of Intel Pentium 4 and Intel Celeron processors. With the
support of a 400MHz or 533MHz processor system bus, DDR (Double Data Rate) 200/266
SDRAM memory or SDR (Single Data Rate) PC133 SDRAM memory, and integrated graphics or
AGP cards, the chipset families provide high system flexibility and scalability.
During Intel’s chipset validation process, it was observed that DDR DIMMs may enter into an
undefined state during a warm reset. The effect of DDR devices entering into an unknown state
occasionally results in a system hang. This issue only occurs during 1-4% of warm resets in failing
systems. This issue has never been seen by Intel when transitioning to or from low power states or
during cold boot.
The most reliable way to successfully transition the system out of a hung state is to initialize the
memory per the JEDEC specification which includes power cycling.
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Technical Background
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2
Technical Background
On Intel® 845 Chipset Family and Intel® 845G Chipset Family based platforms, when warm reset
is initiated, DDR DIMMs may transition into an unknown state. The sequence of events for a
warm reset is as follows:
−
Software writes a value of 06h to the Reset Control register in ICH (offset: CF9h). This is one
of the ways to trigger warm reset. Other ways to trigger warm reset are through use of power
button via the ICH SYS_RESET# pin or external controller access to ICH through SMBUS.
−
ICH asserts PCIRST# to the GMCH.
−
The GMCH asynchronously deasserts CKEs & no longer drives CLK/CLK#.
−
Upon being tristated, the CLK/CLK# lose their differential relationship.
The timing relationship between CKEs being deasserted and the clocks no longer being driven in
conjunction with CLK/CLK# losing their differential relationship causes the DDR DRAMs to go
into an undefined state. When the DRAMs enter into this undefined state, a system hang may
occur during the warm reset. Warm reset events are handled asynchronously, and the outstanding
memory cycles may not be completed prior to the system entering reset.
In order to prevent the system hang from occurring, Intel has developed a BIOS workaround. This
BIOS workaround is able to detect a failing scenario. Upon detecting a failing scenario, the BIOS
workaround will cycle power to system memory. After power is cycled to system memory, the
DRAM devices are initialized per the JEDEC DRAM Specification 2.0 and the Intel Specification
Addendum for JEDEC DDR266 DIMM Specification Revision 1.0 as part of the normal boot
process. The BIOS workaround has been validated by Intel, has shown no platform side effects,
and has been demonstrated to be robust. Additionally, Intel has communicated the specifics of the
BIOS workaround to BIOS vendors. OEMs should contact their appropriate BIOS vendor
regarding availability of a BIOS with the workaround included.
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Summary
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3
Summary
During warm boots, the platform may be subject to an interoperability issue between the chipset
and DDR DIMMs.
The chipsets are functioning as designed. However, the (G)MCH may behave in a manner that is
not addressed by the current JEDEC DRAM Specification 2.0.
An Intel-developed and validated BIOS update is available that mitigates the impact of this issue.
Intel recommends that the OEMs work with their system BIOS vendors to ensure that all Intel 845
Chipset Family and Intel 845G Chipset Family BIOS’s contain the Intel validated BIOS
workaround. Intel has communicated the specifics of the BIOS workaround to BIOS vendors.
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