Microprocesseurs 32 bits intel - AMD (1995

Microprocesseurs 32 bits intel - AMD (1995

Microprocesseurs 32 bits
intel - AMD (1995 - 2003 )
Pentium II, III, 4, Celeron
ATHLON, ATHLON XP
novembre 03
Microprocesseurs 32 bits Intel - AMD ; J. Weiss
1
Évolution des processeurs
Pentium et Athlon
Pentium Pro
Pentium II (Klamath)
Pentium II (Deschutes)
Pentium III (Katamai)
Pentium III (Coppermine)
Pentium 4 (Williamette)
Athlon K7
Athlon K7 (Thunderbird)
Pentium III (Tualatin)
Athlon XP (Palomino)
Pentium 4 (NorthWood)
Athlon XP (Thoroughbred)
Athlon XP (Barton)
novembre 03
Microprocesseurs 32 bits Intel - AMD ; J. Weiss
2
Pentium Pro ~1995
Horloge : 133 – 200 MHz
Front Side Bus : 60 – 66 MHz
Cache L1 : 8KB instruction, 8KB data
Cache L2 : 256-1024KB On-Chip.
Technologie : 0,35 µm.
5,5 millions de transistors
Summary:
The first Intel CPU based on the P6 Microarchitecture. The CPU is contains a onchip L2 cache in the packaging running at
core clock-speed. The CPU is intended for
high end servers/workstations.
novembre 03
Microprocesseurs 32 bits Intel - AMD ; J. Weiss
3
Pentium II ~1997
Horloge : 233 – 450 MHz
Front Side Bus : 66 – 100 MHz
Cache L1 : 16KB instruction, 16KB data
Cache L2 : 512KB half-speed.
Technologie :
• 0,35 µm “Klamath” (233 - 300 MHz).
• 0,25 µm “Deschutes” (300 - 450 MHz).
7,5 millions de transistors
Summary:
Due to the difficulty in manufacturing the Pentium
Pro with on-chip L2 cache, Pentium II moved the
L2 cache to an external cache reside in the “Slot 1”
package. L1 Cache is doubled, and added the
MMX instructions. 100 MHz front side bus is
introduced after 350 MHz models.
novembre 03
Microprocesseurs 32 bits Intel - AMD ; J. Weiss
4
Pentium III (Katmai) ~1999
Horloge : 450 – 600 MHz
Front Side Bus : 100 – 133 MHz
Cache L1 : 16KB instruction, 16KB data
Cache L2 : 512KB half-speed.
Technologie : 0,25 µm.
9,5 millions de transistors
Summary:
Same as Pentium II with added new
SSE SIMD instructions. The “B” model
introduces 133 MHz front side bus.
novembre 03
Microprocesseurs 32 bits Intel - AMD ; J. Weiss
5
Pentium III (Coppermine) ~1999
Horloge : 600 - 1000 MHz
Front Side Bus : 100 – 133 MHz
Cache L1 : 16KB instruction, 16KB data
Cache L2 : 256KB full-speed on die.
Technologie : 0,18 µm.
28 millions de transistors
Summary:
Major improvements from the original
Pentium III, the L2 cache is now fully
integrated onto the CPU die, and the L2
datapath, Associative, and Latency are also
improved. The later model also use revert back
to the more conventional FC-PGA socket
model from Slot 1.
novembre 03
Microprocesseurs 32 bits Intel - AMD ; J. Weiss
6
Pentium III (Tualatin) ~2001
Horloge : 1000 - 1400 MHz
Front Side Bus : 133 MHz
Cache L1 : 16KB instruction, 16KB data
Cache L2 : 256 - 512KB half-speed.
Technologie : 0,13 µm.
• 28 millions de transistors (256K L2)
• 46 millions de transistors (512K L2)
Summary:
Final revision on P6 architecture, with
added data prefetch unit and higher
clock speed. L2 also available in 512 KB
version. This is the first Intel CPU that
uses 0.13 micron copper-interconnect.
novembre 03
Microprocesseurs 32 bits Intel - AMD ; J. Weiss
7
Celeron (Covington) ~1997
Horloge : 233 - 300 MHz
Front Side Bus : 66 MHz
Cache L1 : 16KB instruction, 16KB data
Cache L2 : -.
Technologie : 0,35 µm.
7,5 millions de transistors
Summary:
A tripped down version of the Klamath
Pentium II with no L2 cache on the Slot
1 module. Unsatisfactory performance.
novembre 03
Microprocesseurs 32 bits Intel - AMD ; J. Weiss
8
Celeron (Mendocino) ~1998
Horloge : 300 - 533 MHz
Front Side Bus : 66 MHz
Cache L1 : 16KB instruction, 16KB data
Cache L2 : 128KB full-speed on die.
Technologie : 0,25 µm.
19 millions de transistors
Summary:
Similar to Pentium II Deschutes but
with integrated on-die 128 KB cache.
Also available in Socket 370 package.
novembre 03
Microprocesseurs 32 bits Intel - AMD ; J. Weiss
9
Celeron (Coppermine128) ~2000
Horloge : 533 - 110 MHz
Front Side Bus : 66 - 100 MHz
Cache L1 : 16KB instruction, 16KB data
Cache L2 : 128KB full-speed on die.
Technologie : 0,18 µm.
28 millions de transistors
Summary:
A stripped down version of Pentium III
Coppermine, the Coppermine128 core is
physically identical to Coppermine Pentium
III except half of the L2 cache is disabled
and the front side bus is restricted to 66 MHz
and 100mhz after 800 MHz models.
novembre 03
Microprocesseurs 32 bits Intel - AMD ; J. Weiss
10
Celeron (Tualatin) ~2001
Horloge : 1000 - 1400 MHz
Front Side Bus : 100 MHz
Cache L1 : 16KB instruction, 16KB data
Cache L2 : 256KB full-speed on die.
Technologie : 0,13 µm.
28 millions de transistors
Summary:
Essentially the same as the Tualatin
Pentium III with only 100 MHz front side
bus.
novembre 03
Microprocesseurs 32 bits Intel - AMD ; J. Weiss
11
Pentium 4 (Willamette) ~2000
Horloge : 1300 - 2000 MHz
Front Side Bus : 100 MHz QDR
Cache L1 : 12KµOps instruction, 8KB data
Cache L2 : 256KB full-speed on die.
Technologie : 0,18 µm.
42 millions de transistors
Summary:
The first CPU core with the new
Netburst(P68) architecture. Because of
the fact that it is still manufactured using
the older 0.18 micron technology. The
die of this CPU is extremely large.
novembre 03
Microprocesseurs 32 bits Intel - AMD ; J. Weiss
12
Pentium 4 (Northwood) ~2002
Horloge : 1600 - 3066 MHz
Front Side Bus : 100 – 133 MHz QDR
Cache L1 : 12KµOps instruction, 8KB data
Cache L2 : 512KB full-speed on die.
Technologie : 0,13 µm.
55 millions de transistors
Summary:
The second CPU based on the Netburst
architecture. The processor is now
manufactured using copper 0.13 micron
technology. The L2 cache has been double in
size to 512KB. However, the die size is still
smaller than the Willamette.
novembre 03
Microprocesseurs 32 bits Intel - AMD ; J. Weiss
13
Athlon K7 (Pluto, Orion) ~1999, 2000
Horloge : 500 - 1000 MHz
Front Side Bus : 100 MHz DDR
Cache L1 : 64KB instruction, 64KB data
Cache L2 : 512KB externe.
Technologie :
• 0,25 µm (Pluto).
• 0,18 µm (Orion).
22 millions de transistors
Summary:
The first processor based on the K7
architecture. The L2 cache is located on
the external module similar to
PII/III(katami) and runs at 1/2,3/5, 1/3 of
the core clock speed.
novembre 03
Microprocesseurs 32 bits Intel - AMD ; J. Weiss
14
Athlon K7 (Thunderbird) ~2000
Horloge : 650 - 1400 MHz
Front Side Bus : 100 – 133 MHz DDR
Cache L1 : 64KB instruction, 64KB data
Cache L2 : 256KB on die.
Technologie : 0,18 µm.
37 millions de transistors
Summary:
Similar to the improvement Intel made with
the coppermine core, the thunderbird
integrates the L2 cache into the processor
die and running at full core clock speed. The
thunderbirds produced in Dresden fab are
also the first x86 CPU to use the copperinterconnect.
novembre 03
Microprocesseurs 32 bits Intel - AMD ; J. Weiss
15
Athlon XP (Palomino) ~2001
Horloge : 1333(1500+) – 1666(2100+) MHz
Front Side Bus : 133 MHz DDR
Cache L1 : 64KB instruction, 64KB data
Cache L2 : 256KB on die.
Technologie : 0,18 µm.
37,5 millions de transistors
Summary:
The Palomino core is mainly a reworked
Thunderbird core to reduce power
consumption with added thermal diode. The
core also incorporated the SSE instructions,
increased TLB, and a data prefetch unit.
Externally, the CPU is packaged using the
OPGA array (ie. Plastic) instead of
Ceramic.
novembre 03
Microprocesseurs 32 bits Intel - AMD ; J. Weiss
16
Athlon XP (Thoroughbred) ~2002
Horloge : 1466(1700+) – 2100(2800+) MHz
Front Side Bus : 133 - 166 MHz DDR
Cache L1 : 64KB instruction, 64KB data
Cache L2 : 256KB on die.
Technologie : 0,13 µm.
37,5 millions de transistors
Summary:
Simply a die shrunk of the Palomino core
to 0.13 micron. All the functionalities
remains unchanged.
novembre 03
Microprocesseurs 32 bits Intel - AMD ; J. Weiss
17
Athlon XP (Barton) ~2003
Horloge : 2500+ – 3000+ MHz
Front Side Bus : 166 MHz DDR
Cache L1 : 64KB instruction, 64KB data
Cache L2 : 512KB on die.
Technologie : 0,13 µm.
54,3 millions de transistors
Summary:
Same as Thoroughbred core Athlon XP
with an increase L2 cache to 512KB.
novembre 03
Microprocesseurs 32 bits Intel - AMD ; J. Weiss
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