V - SOI Consortium

Transcription

V - SOI Consortium

2009
2007
Designing Low-power Circuits
with Partially and Fully
Depleted SOI
O. Thomas
SOI Consortium, October the 21st 2009
Santa Clara, California, USA
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O. Thomas, SOI consortium 2009
1
Introduction
Trends of the emerging low-power CMOS
technologies
From “advanced planar SOI devices”
PDSOI, FDSOI, MuGFET
To “3D devices”
MCFET, Monolithic 3D IC
2007
With a particular focus on the Digital and
Memory design to address the decananometer range scaling issues
2
Outline
CMOS scaling issues
Power Management
PDSOI technology for LP applications
FDSOI technology
2007
Film-film SOI alternatives
Summary
3
Outline
CMOS scaling issues
2007
Scaling limitations
Circuit issues
Power management
FDSOI technology
Summary
4
Scaling motivations
Smaller devices = Higher density
Production cost reduction (More dies on a wafer)
More functionality, more memory, more computing resources
(More devices on a die)
Smaller devices = Less Parasitic Capacitances
2007
Faster circuits (τ=RC)
Less dynamic power consumption (P=CV2f)
Better power delay product (PDP)
Constant power density
Smaller devices = More integration
Less discreet devices on the board
Higher signal integrity and more reliability
5
Scaling limitations
In the deca-nanometer range, some physical
parasitic elements become non negligible, leading to:
2007
Electrostatic degradation (SCE, Polydepletion & Darkspace
thickness…)
Quantum effect (Gate oxide tunneling current, S/D direct tunneling,
GIDL)
Transport degradation (Mobility degradation, RSeries…)
Variability (Random dopant fluctuation, Line Edge Roughness)
They give rise to scaling potential limitations
Device geometries (Gate length, Oxide thickness)
Device materials (Gate oxide, Polysilicon gate)
Device configuration (Doping)
Device voltage (VDD, VT)
6
S. Yu, Proc of IEEE 2008
Scaling trends
No more “ideal” scaling
10% to 20% of ION
improvement is needed
per technology node
2007
I ON ∝ µ ⋅
εox VDD ²
Tox
⋅
L
0.7x
0.7x
10V
5V
0.7x
1.2V
Increasing ION while limiting leakage increase
slows down VDD, VT, LG and TOX scaling
7
A. Groove, IEDM 2007
Circuit scaling issues
Operating power not scaling
PDyn = α ⋅ C L ⋅ f ⋅ VDD
2
General scaling (S~1.3)
Fixed-Voltage scaling
S/U3
S
2007
Source: Sub-scaling of VDD
Results: Limiter for battery life time and circuit reliability
Need: Dynamic power management solutions
8
Sources: ST, INTEL
B Tavel, ESDERC 2005
Static power increase
2007
ASIC Power density (W/cm²)
µP Power density (%)
Sources: Tunneling currents and device electrostatic
control degradation (SCE, DIBL, SSw)
Result: Limiter for battery life time of wireless applications
Need: Static power management solutions
9
P. Royannez, DATE 2009
A. Bhavnagarwala, IEDM 2005
Variability
Can be x2 in
2007
speed
Can be x1.2 in
dynamic power
Can be x10 in
leakage
No margin left
Statistical variations @device, gate and circuit levels
Results: Timing & power variations (Power budget, IR
drop), Reliability & robustness degradation (SRAM, FF)
Need: Adaptive or more robust circuit solutions
10
What deca-nanometer scaling involves…
@device level:
2007
Need for a low-VDD to reduce power consumption (low VT)
Need for an increased electrostatic control to reduce OFF drain
current (CG>>CS+CD)
Need for a transport enhancement to improve channel carrier
mobility (Low channel doping)
Need for an intrinsic homogeneous channel to control VT (no RDF)
@circuit level
Need for power management techniques to reduce power
consumption
Need for adaptive circuit solutions to continue power and
frequency scaling
Need for innovative elementary circuit architecture to improve
robustness and compensate imperfections
11
Outline
CMOS scaling issues
Power management
2007
Multi-VT & Multi-TOX CMOS platforms
Low leakage circuit design techniques
FDSOI technology
Summary
12
Sources: ST
Power management trend
Increasing speed w/o degrading power
Process compensation design techniques
Power Supply
Power Management
2007
Process Options
4V
100mA
10mA
Multi Vt CMOS
3V
1mA
2V
100uA
1V
10uA
1985
1990
1995
2000
2005
Product Leakage @125C
(no management)
5V
2010
13
130nm and below CMOS platform offers
LP/GP to manage the triple trade-off {Psat, Pdyn, Speed}
System performance core (LVDD, LTOX)
Stand-by power (VDD, TOX)
Chip interface (HVDD, HTOX)
65nm BULK
2007
B Tavel, ESSDERC 2005
14
RO & SRAM bitcell illustrations
~same delay
EOT=1.8nm
VDD=1.2V
-35%
EOT=1.2nm
VDD=1V
2007
Pdyn versus Pstat for RO FO1
Pstat versus ICELL for SRAM bitcell
Very efficient to improve circuit speed w/o power
consumption degradation
B Tavel, ESSDERC 2005
15
Scaling issue
LVT
IOFF (nA/µm)
10
2007
SVT
1
130nm
HVT
0.1
90nm
65nm
45nm
0.01
0.001
0
200
400
600
800
1000
ION (µA/µm)
Below 65nm, it becomes more and more difficult to
achieve HVT devices
Source: ST
16
Power management
Combination of multiple techniques:
2007
Dynamic power reduction
Massive clock gating
Voltage and frequency scaling (DVFS…)
SRAM, Flip-Flop design
Static power reduction
Low leakage libraries (larger L…)
Power gating (BGMOS, SCCMOS…)
Body biasing
Source Biasing
Retention memory elements (LVDD, UVSS, FBL…)
Split memory array/periphery supply
17
Meijer, ISCAS 2005
Power management
Power gating
VDD
PS
PMOS leakage
cut-off switch
Core
HVT
VDD_CORE
LVT
Core
2007
GND_CORE
LVT
Low IOFF
High IOFF
Low Speed
Low speed
Low IOFF
High IOFF
High Speed
High Speed
Alternatives
NMOS leakage
cut-off switch
HVT
MTCMOS
BGMOS
SCCMOS
VTCMOS…
Effective for logic blocks
18
Power management
VG
BULK
IOFF (log)
Body biasing
VBS=0 VT0
VBS<0 High VT
IOFF
VG
IOFF’
VBS effect VT shift
2007
VB
VGS (V)
High leakage (ISTH) reduction thanks to negative VBS values
Effective for digital and memory elements
19
Power management
BULK
IOFF (log)
Source biasing
VB/GS=0 VT
VB/GS<0 High VT
IOFF
IOFF’
VG
VGS effect
VBS effect VT shift
2007
VS
IOFF’’
VGS (V)
High leakage reduction thanks to negative VGS and VBS values
Well dedicated for retention memory elements
20
Power management
SRAM leakage current distribution
WL=0
VDD
MLL
MLR
MAL
MAR
2007
0
MDL
MDR
VSS
BLR=1
BLL=1
1
Three dominant leakage paths :
1)
2)
3)
Through VDD to ground across the two cross coupled inverters
Through bit-line to ground
Through bit-line and VDD to word-line
21
Power management
SRAM leakage reduction techniques
Lower-VDD
Upper-VSS
VDM
VDD
MLL
MAL
MAR
1
2007
MLL
MLR
MAR
MAL
1
0
MDL
MLR
MDR
VSM
0
MDL
Extra
current
Reduced
current
MDR
VSS
Very efficient for cross-coupled inverters (reduced Ich, Ibody, Ig)
But partially successful for access transistors (extra Ich, Ibody, Ig)
O. Thomas, ICICDT 2008
22
Power management
Floating-BL
VDD
MLL
MLR
MAL
MAR
1
Reduced
current
0
2007
MDL
Extra
current
MDR
VSS
FBL reduced Ibody and Igate of access transistors
FBL balanced Ichannel between the access transistors
23
Power management status
Expanded CMOS platform offer with scaling to manage
power (Multi-VT, Multi-TOX)
Electrostatic control degradation makes it more difficult to
achieve low leakage device (HVT case)
Below 45nm, Low Power CMOS platform trends to “high
speed” devices for LP applications (SVT and/or LVT)
2007
Compensation of the device issues by a combination of
multiple circuit design techniques
Efficiency of most of the design techniques is driven by the
body effect
24
Outline
CMOS scaling issues
Power management
2007
Device benefits
Circuit performances
Leakage power management
FDSOI technology
Summary
25
PDSOI technology
G
Total dielectric
isolation
S
B
D
BOX
Lower junction
capacitance
(εOX=εSI/3)
BULK
VG
VS
VD
Gate
Gate
N++
2007
Source
Body
Drain
Substrate
Temporal VB variation
VT modulation
History effect
N+
N+
Source I
d
Iii
N++
Drain
Buried oxide
Substrate
Initially used for High Speed µP (PowerPC, PS3…) to
improve the power delay product
26
Sources: ST
PDSOI technology
Robustness
Latch-up immunity
SER improvement
Speed/Power
2007
Reduced S/D junction capacitances
Dynamic VT modulation
No reverse body effect in stacked devices
History effect @circuit level
Self Heating
SERBULK/SERSOI
LVT SOI FB
SVT SOI FB
HVT SOI FB
LVT
SVT
Standby power
HVT
Lower junction leakage
Floating body
IOFF vs ION NMOS
(VTSOI_VB=0=VTBULK)
27
Body contacted devices
Body tied structures
Body contacted (BC)
Dynamic Threshold MOS (DTMOS)
Drain
Gate
Drain
Bulk
Gate
Bulk
Body
V
Limiter
2007
Source
Source
Initially proposed to resolve the floating body effect
(Kink effect, History effect)
Provides another degree of design tuning
28
Body contacted devices
Simplest way for suppression of the
history effect
Best ION/IOFF current ratio (DTMOS)
Lower leakage compared with FB
structure
IOFF (log)
Pros
VB=0.6V
DTMOS
VB=0V
VGS (V)
LVT
SVT
Cons
2007
HVT
Layout area penalty
Body voltage limiter
Extra gate capacitance
VTSOI~VTBULK
GC+BC
Must be used carefully, only to
address an issue, mainly in analog,
IOs circuits, power switch…
29
PDSOI technology: Power vs. Speed
Delay Tp (ps/Stage)
FB RO FO1 LG=60nm
30%
BULK 1.2V
SOI 1.0V
20%
SOI 1.1V
SOI 1.2V
2007
Dynamic power (µW/Stage)
30% reduction of PDyn with same speed @reduced VDD
20% of speed improvement @same PDyn
C. Raynaud, ECS 2009
30
PDSOI technology: Leakage
FB RO FO1 LG=60nm
x10
2007
Higher leakage current due to floating body
31
PDSOI technology: Leakage
65nm node, 0.52µm2 bitcell
2
2
0.52µm cell @ 125°C
0.52µm cell @ 25°C
1000
VB reduction with VDD
BULK
Isb (pA)
Isb (pA)
100
SOI
10
BULK
1
Reduced impact ionization
10
0.8
2007
SOI
100
1
1.2
Vdd (V)
1.4
0.8
1
1.2
1.4
Vdd (V)
Due to the FB effect, ISTH dependence on VDD is different
Higher leakage current reduction with VDD
At 125°C, lower leakage due to reduced impact ioniz ation and also
reduced junction leakage in case of SOI (no vertical SD/bulk
junction)
32
Power management
Power Switch alternatives
PS
FB
BT
DTMOS
Charge
Pump
CP
Symbol
Limiter
2007
Pros
Standard
implementation
Low leakage
Best ION/IOFF
Lower
leakage
Cons
Floating body
High leakage
BC area
penalty
BC area
penalty
Design
complexity
Specific PDSOI design
33
Power management
Body effect
65nm BULK
Drain biasing
Source biasing
x2.3
vdd
vdd
gnd
gnd
2007
Higher source biasing efficiency than drain biasing in
BULK due to body effect
Same efficiency in PDSOI (no RBB)
34
Power management
Lower-VDD
Upper-VSS
VDM
VDD
MLL
MAL
MAR
1
2007
MLL
MLR
MAL
MAR
1
0
MDL
MLR
MDR
VSM
0
MDL
Extra
current
Reduced
current
MDR
VSS
In PDSOI, UVSS or LVDD lead to same efficiency
for cross-coupled inverters (no RBB)
35
Power management
Floating-BL
VDD
MLL
MLR
MAL
MAR
1
2007
Reduced
current
0
MDL
Extra
current
MDR
VSS
FBL more efficient in PDSOI technology due to VB
reduction in access transistors
36
Power management
SRAM leakage reduction technique results
2007
Normalized leakage current
1.20
1.00
65nm PDSOI
LVDD
UVSS
LVDD+FBL
0.80
UVSS+FBL
0.60
0.40
0.20
FF, 1.32V, 125°C
0.00
0
0.1
0.2
0.3
0.4
0.5
DELTA (V)
UVSS/LVDD + FBL provide highest leakage reduction
LVDD limited by Ichannel of access transistors mainly in PDSOI
37
Power management and HE
Floating body variations caused by:
Fast mechanism
Slow mechanism
G/D/S coupling capacitance
Charge sharing
2007
Gate
Impact ionization
Generation/Recombination
effects
GIDL, Gate tunneling
Charge variation
Gate (VG)
Source
Body
VG
Drain
Source
(VS)
body
Drain
(VD)
tsi
Substrate
Buried oxide
tbox
Substrate = Back gate (VG2)
38
NMOS Inverter: ARZF
Fast mechanism
Slow mechanism
2
3
VDD
DC010
CDB/2
CDB
CDBx2
MLT
DC1
∆QB
MA T
BLT
VB (V)
DC0
DC100
WL='L'
QB (J)
∆QB
2007
CDBx2
CDB
ML F
QB101
QB011
'H'
QB101+∆VT
QB100
MD T
MA F
'L'
QB001+∆VT
BLF
1
6T SRAM cell
QB010
MD F
CDB/2
Time (s)
Fast process ~ switching time
Slow process: 100µs<T∆QB<1ms ⇒ T∆QB>>TWakeup
39
SRAM leakage reduction technique results
0.62µm 2 cell @25°C
SNM (mV)
250
BULK
200
SOI
150
100
0.8
2007
0.9
1
Vdd (V)
1.1
1.2
Norm. SNM @ RET->RD
1.40
1.20
+20%
-40%
1.00
0.80
0.60
Unstable
in
retention
0.40
0.20
0.00
0
0.1
0.2
0.3
0.4
0.5
DELTA (V)
LVDD
UVSS
LVDD + FBL
UVSS + FBL
In PDSOI, FBL is mandatory to maintain the SNM
UVSS/LVDD+FBL leads to the best leakage reduction
technique
40
PDSOI technology status
@Technology level
Process closed to BULK technology
BULK options available (Multi-VT, Multi-TOX)
@ Design level
2007
Higher speed and/or lower dynamic power
Higher leakage @VDD nominal
Similar leakage @VDD low
BC devices must be used in specific cases (ex: Power Switch)
HE induced dispersions not larger than other sources
Below 65nm node, PDSOI technology becomes an
attractive solution for Low Power Applications.
Designers can take advantage of FB devices for
speed and cut leakage with BC devices
41
Outline
CMOS scaling issues
Power management
FDSOI technology
2007
Device benefits
Circuit performances
Leakage power management
Summary
42
FDSOI technology
PDSOI
FDSOI
G
G
S
B
S
D
BOX
BOX
BULK
2007
D
BULK
Top silicon layer > LG
Silicon under channel is partially
depleted
Floating body effect
High speed µP (PowerPC, PS3)
Top silicon layer ~ 1/3xLG
Silicon under channel is depleted
No floating body effect
Low power application (Watch)
Designed to boost channel electrostatic control
43
V. Barral, IEDM 2007
O. Weber, IEDM 2008
FDSOI technology
Robustness
Latch-up immunity
SER improvement
ESD
Speed/Power
3
Bulk platform
planar FDSOI
2.5
Vt
Reduced S/D junction capacitances
Reduced gate to substrate capacitance
Undoped channel (higher mobility)
No halo implant (higher mobility)
Lower mismatch (RDF)
Self Heating
Series resistance (Thin film)
Setting up Multi-VT (Gate stack, Channel
doping)
A (mV.um)
2007
2
ST 45nm
[10]
IBM alliance 32nm
[3]
ST 65nm
[11]
IBM 90nm [9]
Intel 65nm
[7]
Intel 45nm
1.5
UTBSOI
LETI [1]
1
square : V =50mV
d
circle: V =1V
Standby power
Good channel electrostatic control
Lower junction leakage
0.5
10
d
20
30
40
50
60
Gate length L (nm)
Best matching ever reported
44
FDSOI technology: Power vs. Frequency
16bit Han-Carlson adder
Simulation results (no back-end capacitances)
14
FDSOI
5
FDSOI L=1um, TOX=1.8nm
12
BULK 45nm
BULK L=1um, TOX=1.9nm
10
4
CGG (fF)
Normalized Delay
6
x2.9
3
2
8
Accumulation
6
4
2007
x1.9
1
0.8
1
Depletion
2
0
0.6
Strong
Inversion
1.2
0
-1.20
-0.80
-0.40
0.00
0.40
0.80
VGS (V)
VDD (V)
Larger speed improvement at low VDD due to better SSw
and lower average gate capacitance (no accumulation)
45
1.3
σ (VT)
1.2
VDDmin @125C°° (V)
σint
90 nm bulk
σext
65 nm bulk
45 nm bulk
32 nm bulk
65 nm FD-SOI
σint σ (VT)
σext
2007
1.1
32 nm FD-SOI
Standard deviation (a.u.)
VDDmin
0.8
0.6
2
(bulk)
0.9
0.7
1
Lower VDD
thanks to
lower σVT
VDDmin
1.0
45 nm FD-SOI
0
VT (ext, 25°°C)=0.4V
inter-die 6σ (VT )
Standard deviation σ (VT ) (a.u.)
FDSOI technology: Low VDD
K. Itho, AVLSIWS 2005
3
(FD-SOI)
2
bulk
σ (VT )
90
65
1
FD-SOI
45
32
0
Technology (nm)
Lower VDDMIN thanks to lower VT variations
46
FDSOI technology: Low VDD
SRAM cell
2007
Better tradeoff between density and VDDMin
thanks to the FDSOI AVT record and low DIBL
47
Electrostatic booster
G
SS@VDS=VDD (mV/dec)
UTBOX-FDSOI device
C. Gallon, SOI conf. 2006
C. Fenouillet-Beranger, ESSDERC 2009
70
w/o BP
65
60
TIN
LDD
LDD
10nm
0
D
Back plane P+
2007
Limits the fringing
field effects
Limits the bulk
depletion thickness
100
150
LG=45nm
80
BOX
50
TBOX (nm)
90
DIBL (mV/V)
S
with BP-p
LG=1µm
70
60
50
40
30
20
with BP-p
10
w/o BP
0
0
50
100
150
TBOX (nm)
Reducing the BOX thickness with ground plane (GP)
provides much better VT control
But there is a trade-off to find with the SS
degradation
48
UTBOX-FDSOI device
C. Fenouillet, SSDM 2008
V. Barral, IEDM 2007
VT for undoped thin film SOI device is determined
by the metal gate workfunction
Set-up Multi-VT is one of the major issues
Some solutions exist:
2007
Co-integrate different metal gate materials (different work
function)
Co-integrate different gate thicknesses
Dope the silicon film (like in BULK)
But these solutions lead to:
Process complexity increase
Process cost increase
VT variability increase
Performance decrease
49
J-P. Noel, ESSDERC. 2009
UTBOX-FDSOI device
High manufacturability Multi-VT concept
SVT
HVT
G
G
D
S
BOX
p-type
Substrate
G
D
S
BOX
p-type
Substrate
LVT
G
D
S
BOX
Substrate
G
D
S
BOX
n-type
Substrate
D
S
BOX
n-type
Substrate
2007
VDD
VDD
VT options can be obtained with different Back Plane
doping types (n and p) and voltages (0V and VDD)
Concept based on standard FDSOI process flow
50
UTBOX-FDSOI device
VT options
VT variations
nMOS
VBP-S
0V
VDD
BP-n
SVT
LVT
BP-p
HVT
SVT
w/o BP
SVT
SVT
VT@VDS=0.1V (mV)
700
High-VT
600
500
ΔVT=86mV
400
BP-p (Vbp-s=0V)
BP-p (Vbp-s=Vdd)
300
W/O BP
200
100
nMOS
0
0
50
100
150
TBOx (nm)
pMOS
700
|VBP-S|
0V
VDD
BP-n
HVT
SVT
BP-p
SVT
LVT
w/o BP
SVT
SVT
VT@VDS=0.1V (mV)
2007
LG=1µm
ΔVT=80mV
600
500
LG=1µm
BP-n (Vbp-s=0V)
400
Low-VT
300
BP-n (Vbp-s=Vdd)
W/O BP
200
100
nMOS
0
0
50
T
100
(nm)
150
BOx
51
UTBOX-FDSOI device
Saturation of IOFF
1.E+09
Drain current
1.E+08
700
1.E+07
1.E+06
ION/IOFF
ION (µA/µm)
600
500
1.E+04
400
1.E+03
300
1.E+02
1.E+01
200
0
IOFF (A/µm)
1.E-06
100
150
LG=45nm
LG=45nm
1.E+00
0
50
100
150
TBOx (nm)
HVT
SVT (BP-p)
1.E-07
HVT
SVT
SVT (w/o BP)
LVT
Strong increase of IOFF
TBOx (nm)
2007
1.E-05
50
Optimum
TBOx=30nm
1.E+05
SVT (BP-n)
1.E-08
SVT (w/o BP)
1.E-09
LVT
1.E-10
1.E-11
1.E-12
TBOx=30nm
HVT
SVT
LVT
LVT/HVT
ION (µA/µm)
413
488
558
1.35
IOFF (pA/µm)
1.4
13.5
426
304
ION/IOFF (106)
295
36
1.3
-
ION current variations similar
to 45nm BULKO.technology
Thomas, SOI consortium 2009 52
0
50
100
TBOx (nm)
150
Power management: UTBOX-FDSOI
Substrate voltage control
G
D
S
2007
G
IGIDL, IPN, IG
Substrate
D
S
BOX
p-type
Substrate
No substrate leakage in UT2B-FDSOI
Bulk voltage can be controlled easier
53
Power management: UTBOX-FDSOI
Back gate effect
1.E-08
IOFF (A/µm)
1.E-09
TBOX=150nm
G
1.E-10
D
S
BOX
p-type
1.E-11
1.E-12
Substrate
TBOX=10nm
2007
1.E-13
-1 -0.8 -0.6 -0.4 -0.2 0
0.2 0.4 0.6 0.8
1
VBP (V)
Increase of BG control on the leakage reduction with
TBOX thinning
Saturation of BG effect due to leakage at the back
interface coming from GP configuration
54
FDSOI technology status
@Technology level
Process different to BULK technology
Multi-VT options available in UT2B-FDSOI
@ Design level
2007
Reduced dynamic power (lower device capacitances)
Reduced static power (High K + subthreshold slope)
Reduced delay (same delay @ reduced VDD)
Lower Random variability (No channel doping)
Easier BULK voltage control (No IBB)
55
Outline
2007
CMOS scaling issues
Power management
FDSOI technology
Device benefits
SRAM cell design
Summary
56
Multiple-gate FET devices
T. Ernst, ICICDT 2008
Electrostatic booster
w
sourcet
w
Gate
BULK
source
w
FDSOI
w
Gate
t
source
2007
DGFET or FinFET
Gate
Source
Trigate or Nanowire
L
SS (mV/dec) or DIBL (mV/V)
Gate
140 p-MCFET
120
100
Slope
80 Sub-threshold
60
40
Leff = 50nm
20
DIBL
0
0
100 200 300 400 500
Channel Width, W(nm)
140
Surrounding gates provide much better short
channel effect control
57
Independent multiple-gate FET devices
DGMOS and FinFET
Dynamic VT shift thanks to interface coupling
Dynamic variation of ION per unit area (1 or 2 channels)
ION 2 channels
0.65
VBG = 1V
Tox1= T ox2=1.2nm, Tsi=15nm
2007
Vth1 (V)
S
VTFG
D
Interface coupling
Log(IDS) (A)
0.60
G1
Vg1=1.2V
0.55
0.50
G2
x5
VBG = VFG
ION 1
channel
0.45
VBG = 0V
0.40
0.0
0.2
0.4
0.6
0.8
1.0
1.2
IOFF
Vg2 (V)
VG
BG
VFG (V)
Designers can take advantage of the second gate for
performance and robustness circuit improvement
B. Yu, IEDM 2002
58
3D stacking channel device
E. Bernard, VLSI 2008
MCFET and Stacked nanowires
Based on stacked silicon films with undoped channel
surrounded by gate
Source and drain are raised up to top of upper channel
connecting all channels together
TiN
HM
Si
2007
GAA:
channels
1 and 2
G3
GAA:
channels
3 and 4
G2
Bottom S
FD-SOI:
channel 5
HfO2
TSi = 10nm
Poly-Si
G1
L = 50nm
D
Si sub.
BOX
TEM picture of 5 channels 60nm gate
length on nMCFET
TEM picture of 3 Si nanowires
Enhancement of ION current per layout unit
59
E. Bernard, VLSI 2008
MCFET technology experimental results
Log(I) (A/µm)
10 -3
10 -4
2007
10 -5
10 -6
10 -7
10 -8
10 -9
10 -10
VDD=-1.2V L=50nm
VDD=-50mV 5 channels
10
VDD=1.2V
-8
LSTP
VDD=50mV
10
-9
Planar Single Gate 1.2V
Planar Single Gate 1.1V
Planar Single Gate 1V
FinFET like 1.2V
pMCFET
IOFF (A/µm)
10 -1
10 -2
nMCFET
ION=1.32mA/µm
ION=2.27mA/µm
IOFF=16.8pA/µm
IOFF=16.4pA/µm
SS=65.8mV/dec
SS=63.3mV/dec
DIBL=20.4mV/V
DIBL=20.3mV/V
VT=470mV
10 -11 VT=-570mV
10 -12
10 -13
-1.6 -1.2 -0.8 -0.4 0.0 0.4 0.8 1.2
VG (V)
Planar MultiGate 1V
10
Planar MultiGate 1.2V
-10
MCFET 1.2V
10
-11
10
-12
ITRS 2005 : 65, 45, 32, 22nm nodes
1.6
0
500
1000 1500 2000 2500 3000
ION (µA/µm)
3D structure based on undoped channels enhance IOFF to
as low as 16 pA/µm and ION to as high as 2.27mA/µm
60
T. Ernst, ICICDT 2008
VG2=1.2V
Si
Spacer
SiO2
2007
BOX
a)
b)
T1
VG2=0V VG1=1.2V
Gate 2
Gate 1
VG1=1.2V
Double Drive
Gate 1 threshold voltage V
Single Drive
(V)
ΦFET
1
0.8
0.6
0.4
0.2
Channel 2
acc.
0
Channel 2 Channel 2
depleted
inversed
-0.2
-2
-1.5
-1
-0.5
0
0.5
Gate 2 voltage V
(V)
G2
1
The concept of independent gate can be adapted to
multi-channels and stacked nanowires
61
Monolithic 3D IC technology alternative
Monolithic 3D IC technology
Based on stacked undoped silicon film MOS
-0.2
pMOS
pMOS
VTH TOP MOS (V)
pMOS
-0.3
TILD
-0.4
2007
nMOS
VTH (VG,BOT=VDD)
VTH (VG,BOT=0)
-0.5
0
25
50 75 100 125 150 175 200
ILD thickness (nm)
3D Contact @the transistor scale (Alignment~σ=10nm)
Independent device optimization
Dynamic VT modulation
62
Monolithic 3D IC technology alternative
2 inputs NAND gate example
NMOS/PMOS
CMOS/CMOS
4 x M2 pitch
2D
P. Batude, VLSI 2009
9 x M2 pitch
-48
%
3 x M2 pitch
-30
%
2007
4 x M2 pitch
8 x M2 pitch
13 x M2 pitch
4 x M2 pitch
63
SRAM yield
SRAM represents a large fraction of chip area (50%) and chip
transistors (80%)
100ppm fails for 10Mbit/chips
SRAM acceptance criteria: µ/σ>6-7
SRAM more vulnerable to process variations and VT mismatch
than logic circuits
Minimum size devices are used
No averaging effect as in logic data paths
SRAM designs push rules aggressively (density):
2007
Smallest geometry transistors
Break FE/ME/BE design rules
SRAM uses (performance):
Low-swing signaling for better performance and lower power
Circuits based on path-matching and/or race conditions
Chip Size, Leakage, Variability, Voltage Scaling,
Performance and Cost are driven by SRAM
64
Ak
Focus on Bitcell
Storage
array
Word line
Bit line
AL-1
Row decoder
SRAM yield
415
60
95
55
85
360
90
140
105
45
BL0
2007
BLk-1
60
60
140
40
Sense Amplifier
Ak-1
A0
Column decoder
Data bus
65
SRAM yield
Key technical specifications:
2007
Adequate cell stability for reliable operation
Adequate cell write-ability for reliable operation
Maximum drive current to achieve high speed
Minimum static current for low standby power
Minimum cell size for highest density
Good manufacturability
These various specifications are conflicting
Cell device sizes are derived from proper
balance of each of these needs
66
SRAM yield
SNM versus WM
WL
PR=βML/ βMA
MLL
MLR
MAL
MAR
L=1
R=0
MDL
MDR
BLR
BLL
2007
CR=βMD/ βMA
SNM: Make sure that internal node R=0 does not go high
enough to turn on MDL
WM: Make sure that internal node L=1 goes low enough to
turn on MLR
67
L. Chang, VLSI Circuit 2007
Z. Liu, VLSI Circuit 2008
SRAM yield
Dual port bit-cells (1R1W)
9T SRAM bit-cell
8T SRAM bit-cell
RWL
BLR
RBLL
WBLR
2007
WBLL
BLL
WWL
WWL
RWL
Cells nodes are not disturbed during read
stability problem eliminated
Read and Write mechanisms are decoupled
write-ability problem eliminated
68
SRAM yield
Dual port bit-cells (1R1W)
2007
Pros
Read stability as good as retention
stability
Rectangular layout approach (8T)
Good variability solution
Good scaling
Low VDDMIN
System performances improved
Cons
30% of bit-cell area penalty
Change all existing array designs
and floorplans
L=25nm; 0.1998µm² +30%
SNM 1.76x
SNM 2x
Higher stability at the expense
of density
69
M. Yamaoka, VLSI Circuit 2004
Z. Guo, ISLPED 2005
O. Thomas, ISCAS 2007
K. Endo, IEDM 2006
SRAM yield
Independent double gate bit-cells
6T-Feed Back
WL
RWWL
BLL
BLL
BLR
WL
BLR
BLL
6T-2WL
BLR
6T-BG tied to source
2007
WWL
Back gate biasing for static or dynamic cell ratio
modulations
{WM,SNM} trade-off improved
70
Functionality
SRAM yield
RNM
1.0
RT
0.8
SNM
0.6
0.4
Independent double gate bit-cells
2007
Pros
Stability improved (SNM + NBL)
Good variability solution (Undoped
channel)
Low leakage
Low VDDMIN
Cons
ICELL reduced
Back-gate contact area penalty
Change all existing array designs
and floorplans (6T-2WL)
Asymmetrical devices (6T-FB)
Higher stability at expense of
performance
0.2
WT
WM
0.0
ICELL
NBL
ILEAK
6T
6T-2WL
Performance
Functionality
RNM
1.0
RT
0.8
SNM
0.6
0.4
0.2
WT
WM
0.0
ICELL
Performance
NBL
ILEAK
6T
6T
6T Hitachi
BGTS
71
O. Thomas, ESSDERC 2008
SRAM yield
Multi-channel bit-cell
WL
VDD
MLLT
ML
ML
F
ML
R
MAT
MA
L
'L'
R=‘0’
'H'
L=‘1’
MD
MDL
2007
BLF='H'
BLT='H'
MAF
MA
R
Number of channels
per device
MD
MD
F R
T
V(SM)
BLL
BLR
3D bit-cell sizing by adjusting number of channels per
device
{SNM, Density} trade-off improved
72
1.6
SRAM yield
Normalized variation
1.4
Multi-channel bit-cell
2007
Reference
1.0
-27%
0.8
RT
0.6
CBL
0.4
Pros
High density
Conventional bit-cell layout
Conventional array designs and
floorplans
Low leakage (MCFET technology)
Better power delay product
Cons
Process flow
CWL
0.2
0
1
3
4
5
6
MCA
2.0
1.8
1.6
1.4
1.2
+28%
1.0
Reference
0.8
0
1
2
3
4
5
6
MCA
MA
Charac. 32nm
Bit-cell electrical performance
improved w/o area penalty
2
MA
SNM improvement
1.2
Conv.
Opt.
Comp
SNM (mV)
203
237
+17%
WM (mV)
471
441
-6%
NBL (x10-6)
1.2
1.42
+19%
ILEAK (nA)
0.35
0.27
-23%
RT (ps)
130
129
-1%
CBL (fF)
0.6
0.4
-33%
CWL (fF)
2.0
1.3
-27%
73
S-M. Jung, VLSI 2005
SRAM yield
3D stack device bit-cell
2007
3D device stacking
Bit-cell
density drastically improved: 84F216F2
74
SRAM yield
WL
Boosted ‘1’
discharge in
write mode
MLL
MLR
R=0
MDL
MDR
BLR
2007
BLL
L=1
Improved
NMOS leakage
ICELL maintained and
Weakened VR in
read mode
MAR
3D device stacking
Density improved
Back gate biasing for dynamic cell ratio modulations
{WM,SNM} trade-off improved
75
SRAM yield
2007
Pros
High density
Rectangular bit-cell layout
approach
Low leakage (Thin film
technology)
Low VDDMIN
Cons
3D layout
Process cost
Power-efficient, improvedstability and increased-density
without read cell current
penalty
Bottom
Top
0.290µm²
Lg=40nm
SNM (mV)
WM (mV)
ICELL (µA)
IOFF (pA)
NBL (x106)
Area (µm2)
2D
229
381
33
14.5
45.2
0.365
3D
252
386
33
12.7
50.6
0.29
Comp
+10.4%
~
~
-12.3%
+12%
-20.4%
76
Emerging technology trends
Thin film to increase electrostatic control
Undoped film to reduce sensitivity to dopant
fluctuation effects
Multiple or surrounding gates to provide much
better short channel effect control
2007
Independent gate concept to give more design
flexibility
3D stacking of channels to increase ION per layout
unit
3D stacking of circuit to increase circuit density
77
Emerging devices allow
One additional degree of design tuning
Independent DG FET UT2B-FDSOI, DGMOS, FinFET,
3DMonolithic
SRAM stability improvement
Power management (VT modulation)
Higher density
2007
MCFET, 3DMonolithic
78
Outline
2007
CMOS scaling issues
Power management
FDSOI technology
Summary
79
Summary
CMOS scaling challenges give rise to:
New materials (High-K gate metal)
New transistor concepts (based on undoped thin film devices)
New elementary cell architectures
SOI key advantages regarding Power/Delay:
Reduced dynamic power (lower device capacitances)
Reduced static power (Junction leakage + subthreshold slope)
Reduced delay (or same delay @reduced VDD)
Lower variability for undoped thin film
2007
Emerging devices key benefits:
Added degree of design tuning
Higher density
80
Summary
Power management
Techno.
UTBOX
Multiple
gate
PDSOI
FDSOI
Multi-VT
☺
Process
complexity
☺
Process
complexity
Multi-VDD
☺
☺
@device
☺
level
☺
☺
☺
☺
Poor
impact
☺
☺
☺
☺
☺
☺
☺
PM
2007
Dynamic Voltage
scaling
Body biasing
Source biasing
Total dielectric isolation between voltage
island
-
81
Acknowledgement
CEA-LETI: J-P. Noel, A. Valentian, M.
Belleville and many other
STMicroelectronics: P. Flatresse, F. Boeuf
CEA-LETI laboratories: LTMC, LDI, LME
2007
CEA-LETI facilities
82
2007
Thank you for your
attention
83

V - SOI Consortium

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