How to get 23 bits of effective resolution from your 24

®
HOW TO GET 23 BITS OF EFFECTIVE RESOLUTION
FROM YOUR 24-BIT CONVERTER
By Bonnie C. Baker
The ADS1210 and ADS1211 are precision, wide dynamic
range, ∆Σ A/D converters that have 24 bits of no missing
code and up to 23 bits rms of effective resolution. Because
of the nature of the ∆Σ design architecture the circuit
designer has control over more of the variables and interface
options in the A/D’s conversion process than is realizable
with other converter architectures. These options are digitally implemented and include analog input configuration,
oversampling, calibration and digital protocol control. Consequently, these A/D converters can service a wide variety of
applications, including high precision, high speed, and low
power.
Although the ∆Σ converter absorbs the computational
overhead of the digital filtering function, there is a slight
variation for digital output to digital output. The accuracy of
the digital output code is affected by the cumulative noise at
the time of the conversion. This noise can be generated by
the circuit and injected into the A/D converter through the
input pins, reference pin or power supply connections.
Alternatively, the noise can also be generated by the device
itself. Effective resolution is defined as the statistical standard deviation (Vrms) of multiple conversions. A sample
size of 256 was used to characterize the ADS121x family of
products. Smaller sample sizes are also appropriate.
There is the subset of conditions that must exist before
23 bits rms of resolution can be achieved with the
ADS1210/11. The manipulation of these A/D functions as
well as practical layout recommendations are discussed in
this application note.
Although noise is a random event and any amplitude is
theoretically possible, the occurrence of each output over time
can be reliably predicted with the Gaussian distribution statistical model. When the rms value is multiplied by twice the
crest factor, a peak-to-peak equivalent can be computed. The
Gaussian distribution, shown in Figure 1, illustrates that the
likelihood of large values decrease with increased magnitude.
The probability of exceeding a value above the rms (one
standard deviation) can be anticipated with a crest factor
(peak/rms). Peak-to-peak values can be predicted with a 2x
crest factor. Figure 1 illustrates the probability of a specific
output deviation for the average output vs the 2x crest factor
multiple. For instance, with an effective resolution of 1µVrms,
the probability of a sample exceeding ±2.625µV (2x crest
factor = 5.25) from the average output is 0.01. If a 2x crest
factor of 6.6 is applied, the probability of the output exceeding
±3.3µV of the average output is 0.001.
23-BITS rms OF EFFECTIVE RESOLUTION DEFINED
Effective number of bits or effective resolution is a term that
was developed with the arrival of the 16+ bit converters.
These high resolution converters were capable of outputting
more bits than could accurately be digitized with one conversion. With careful layout practices, this degree of uncertainty was and still is predominately a consequence of
device noise. Multiple conversions, along with mathematical manipulation, reliably produces a higher effective resolution at the expense of overall conversion speed. The
addition of a DSP or µC type device is required in the
application to accomplish this type of performance improvement. The topology of ∆Σ converter relieves the board level
designer of the intensive DSP software design work by
incorporating the over sampling and digital filtering inside
the A/D chip.
P-P NOISE CALCULATIONS FROM RMS
1.0
Probability of Higher Peaks
0.1
The high resolution ∆Σ converters, such as the ADS121x
family from Burr-Brown, advertise an effective resolution
up to 23 bits rms in a 10Vp-p Full-Scale-Range at a 100Hz
data rate. This translates to 0.975µVrms of effective resolution. For the remainder of this discussion, “effective”
defines the rms digital output of the ADS1210/11 when
configured in a full-scale input range of 10V and a Programmable Gain setting of one. This performance exceeds other
A/D converter topologies, such as the SAR (Successive
Approximation) designs. As an extra bonus, the ∆Σ converter applications are less expensive than the precision
SAR converter applications.
©
1997 Burr-Brown Corporation
SBAA017
0.01
0.001
0.0001
0.00001
0.000001
0.0000001
0.00000001
0.000000001
2
3
4
5
6
7
8
9
10
11
12
2x Crest Factor (Vp-p/Vrms)
FIGURE 1. When converting rms noise to peak-to-peak
noise a crest factor can be used as a multiplying constant
which predicts the probability of peaks occurring beyond the
peak-to-peak noise calculation.
AB-120
1
Printed in U.S.A. September, 1997
1
3
4
PROGRAM THE CONVERTER’S TURBO MODE
AND DECIMATION RATIO
The 2x crest factor constant can be chosen to meet the
application need, however, 6.6 is the standard that BurrBrown has chosen to use to define “Noise Free Bits”. With
this 2x crest factor,
The ADS1210/11 default data rate is (850 x XIN/107)Hz. For
example, if the external clock to the A/D converter (XIN) is
10MHz, the default data rate would be 850Hz. The data rate
of the A/D converter is easily measured by putting a oscilloscope probe on the DRDY pin. This default data rate is
achieved with a decimation ratio of 23 (decimal) and a turbo
mode of one. When the ADS1210/11 is programmed in this
manner, the expected effective resolution is approximately
12 bits rms (given XIN = 10MHz). Before 23 bits rms of
effective resolution can be realized, the turbo mode and
decimation ratio must be re-programmed into the A/D
converter. Table III lists the suggested turbo mode and
decimation ratio vs external clock (XIN) that is required to
get 23 bits rms effective resolution.
Noise Free Bits = Effective bits rms – 2.723 bits.
Using the ADS1210/11 as an example, Table I illustrates
the relationship of bits rms (FSR = 10V), Vrms, p-pV and
Noise Free Bits (FSR = 10V). In this table the data rate is
defined as the frequency of the digital output data produced
by the converter. The Turbo Mode (in this case, 16) is an
ADS1210/11 feature that is used to increase the modulator
sampling rate by 2, 4, 8 or 16 times normal. An increase
in sampling rate is equated with an increase in effective
resolution.
EFFECTIVE
EFFECTIVE
RESOLUTION
DATA
EFFECTIVE RESOLUTION
(p-pµVrms,
RATE (Hz) BITS rms
(µVrms)
2x crest factor = 6.6)
40
50
60
100
1000
23.0
23.0
23.0
22.5
20.0
1.0
1.0
1.0
1.4
7.8
6.6
6.6
6.6
9.24
51.48
It is useful to note that the setting for the Programmable
Gain Amplifier (PGA) inside the ∆Σ converter is always
configured as equal to one if 23 bits rms of effective
resolution is the desired goal.
EFFECTIVE
NOISE
FREE BITS
20.28
20.28
20.28
19.78
17.28
TABLE I. Using the ADS1210/11 as an example, the various
ways of calculating the accuracy of the conversion process
are shown.
NOISE
LEVEL
(µVrms)
TURBO
MODE
RATE = 2
TURBO
MODE
RATE = 4
TURBO
MODE
RATE = 8
10
20
40
50
60
100
1000
2.9
4.3
6.9
8.1
10.5
26.9
6909.7
1.7
2.1
3.0
3.2
3.9
6.9
1354.4
1.3
1.7
2.3
2.4
2.6
3.5
238.4
1.3
1.6
1.8
1.9
2.7
46.6
EXPECTED
DATA RATE (Hz)
10MHz
5MHz
2.5MHz
16
8
16
5200 to 8000
7812
7812
40Hz to 60Hz
10Hz
10Hz
The best layout approach is to power the analog section of
the A/D converter from one supply and the digital section
from a separate +5V supply. In this configuration, the analog
supply should come up first insuring that the substrate is not
reverse biased causing a latch condition. Good decoupling
practices should be used for the A/D converter on both the
analog and digital supplies. A 1µF to 10µF capacitor, in
parallel with a 0.1µF ceramic capacitor is recommended. All
decoupling capacitors should be placed as close to the
device as possible, particularly the 0.1µF ceramic capacitors. For either supply, high frequency noise will generally
be rejected by the digital filter except for integer multiples
of the modulator frequency. In particular, the analog supply
should be well regulated and with low noise. The Power
Supply Rejection vs Frequency graph shown in Figure 2.
With the ADS1210/11, the turbo mode function allows the
user to program the over sampling speed of the converter.
The turbo mode function is the key to achieving 23 bits rms
of effective resolution. As the turbo mode is increased, the
effective resolution is also increased. Table II shows the
relationship between Turbo Mode and various data rates.
TURBO
MODE
RATE = 1
ACCEPTABLE
DECIMATION
RATIO(s)
FOLLOW GOOD GROUND AND POWER
PLANE LAYOUT PRACTICES
10V
 6. 02 • ER in bits rms + 1. 76 


20
10
DATA
RATE
(Hz)
RECOMMENDED
TURBO MODE
TABLE III. The A/D converter’s turbo mode and decimation
ratio must be re-programmed from its default setting in order
to achieve 23 bits rms of effective resolution.
The translation from effective bits to effective resolution or
visa versa is:


10V
20 • log 
 – 1. 76
 ER in Vrms 
ER in bits rms =
6. 02
ER in Vrms =
EXTERNAL CLOCK
FREQUENCY, XIN
TURBO
MODE
RATE = 16
The DEM-ADS1210/11 can be used to illustrate the importance of these grounding and power supply practices. Since
the segregation of the analog and digital supplies on the
power plane and ground plane is the same, the ground plane
is shown in Figure 3 and used for this discussion. The
device’s analog pins (1, 2, 3, 4, 5, 6, 7, 19, 20, 21, 22, 23, and
24 in the case of the ADS1211) are all on the analog ground
and power plane. The device’s digital pins (8, 9, 10, 11, 12,
13, 14, 15, 16, 17, and 18 in the case of the ADS1211) are
1.0
1.0
1.0
1.4
7.8
TABLE II. This table demonstrates that the performance of
the ADS1210 and ADS1211 can be adjusted with changes in
Turbo mode and decimation ratio.
2
FIGURE 3. The DEM-ADS1210/11 demonstration fixture analog and digital power planes are separated as shown above.
the board layout for these high resolution ∆Σ converters. If
the A/D converter plus a few logic chips were the only parts
on the board, the ground and power plane layout restrictions
can be relaxed. If there is a minimum amount of glue logic
in the layout, the A/D converters can achieve 23 bits of
resolution with one ground and power plane. The key to a
successful 23-bit system is to keep the digital return currents
away from the analog front end of the circuit. Pay particular
attention to the clocking network’s current paths and high
frequency coupling. Extra caution should be taken with the
surface mount versions of the ADS1210 and ADS1211.
Since the substrate of the chip is physically closer to the
board than it would be with a plastic DIP, the power plane
and ground plane should be removed from underneath the
chip.
PSRR vs FREQUENCY
85.0
PSRR (dB)
80.0
75.0
70.0
65.0
0.1
1
10
100
1k
10k
100k
Frequency (Hz)
The DEM-ADS1210/11 board lends itself for easy experimentation in exploring different power layout configurations. The results are summarized in Table IV.
FIGURE 2. Good grounding practices and layout practices
suggest that the analog and digital power planes be separate.
The ADS1210 and ADS1211 power supply rejection versus
frequency are shown here, emphasizing that noise reduction
techniques should be applied to the power supply busses.
It is useful to note that the DEM-ADS1210/11 has a fair
amount of logic on the board, including two µP and an array
of memory chips. The data in Table IV illustrates the affects
of digital noise coupling into the analog signal path and
consequently increasing the noise floor.
all on the DUT (Device Under Test) digital ground and
power plane (see Figure 3). The digital pins of the A/D
converter interface to the “DUT Controller” µP, 8xC51 (U4).
This µP and the “Memory Controller” µP (8xC51, U5) along
with the digital memory chips have their own ground and
power plane that are partially partitioned from the DUT
digital ground and power plane. With this layout, the current
paths of the digital portion of the board are steered towards
the power connector instead of past the digital side of the A/
D converter. Power is supplied to the board via the analog
power supply connector, P4, and the digital supply connector, P5.
SELECT THE RIGHT EXTERNAL CLOCK SOURCE
The type of clock that is used with the ADS121x does have
an effect on the noise performance of the device, particularly
when calibration is used. The noise seems to increase as the
clock gets further away from a perfect sine wave. For
instance, a square wave that is rich in harmonics can cause
the most problems.
A square wave is rich is harmonics which are easily coupled
from trace-to-trace or from the digital-to-analog planes.
Careful layout may reduce the affects of this noise source. In
terms of calibration, the self calibration process of the
At first glance, this layout would suggest that the demo
board designer has gone to extraordinary efforts to optimize
3
EFFECTIVE
RESOLUTION
(µVrms)
EFFECTIVE
RESOLUTION
(Bits rms)
Short analog and DUT digital ground and power
at the chip by shorting pin 6 (AGND) to pin 12
(DGND) and pin 19 (AVDD) to pin 13 (DVDD).
18
18.8
Short analog and DUT digital ground at the
chip by shorting pin 6 (AGND) to pin 12 (DGND).
18
18.8
Short analog and DUT digital power at the chip
by shorting pin 19 (AVDD) to pin 13 (DV DD).
18
18.8
Short analog and DUT digital ground and power
at the edge of the board by inserting a shorting
bar in R1 (for ground short) and CRN2
(for power plane short).
5
20.6
Short analog and DUT digital ground at the
edge of the board by inserting a shorting bar
in R1.
5
20.6
Short analog and DUT digital power at the edge
of the board by inserting a shorting bar CRN2.
5
20.6
Connect the power to the board from the bench
power supply with four one inch wires.
1
23
TEST CONDITIONS
nodes. In these application, operation should improve if a
system calibration is used.
AN EXTERNAL VS INTERNAL 2.5V REFERENCE
An external reference is recommended for the circuit design
where 23 bits rms effective resolution is the design goal. The
recommended circuit configuration is shown in Figure 4. In
this circuit a REF1004-2.5, 2.5V reference from Burr-Brown
is used. This same reference chip along with the support
circuitry is implemented on the demonstration fixture for the
ADS1210 and ADS1211, (DEM-ADS1210/11). The internal
reference for the device will usually provide at most
20 bits rms, regardless of the other measures to achieve
optimum performance. Since the ADS1210 and ADS1211
reference is a CMOS reference, it has more noise than an
equivalent bipolar reference. The effective resolution graphs
included in the product data sheet for the ADS1210/11
products were generated with an external reference
(REF1004-2.5).
TABLE IV. ADS1211, XIN = 10MHz, data rate = 60Hz,
Turbo Mode = 16, PGA = 1, expected number
of effective bits rms = 23.
SPECIAL CARE WITH THE INPUT PINS
In terms of the differential analog inputs, there is one pair
inputs with the ADS1210 and four pairs with the ADS1211.
Three techniques can be used to reduce the input noise to the
converter at these pins. A primary consideration is to make
converter disconnects the inputs from the input pins and
performs the self calibration. Once the device goes into
normal operation, the noise from a non-perfect sine wave
oscillator can be coupled into the high impedance input
22
23
24
1
2
3
4
5
7
Analog Power +5V
Supply
6 AGND
R13
0Ω
19 AV
DD
J4 1
R8
50kΩ
AIN4P
AIN4N
AIN3P
AIN3N
AIN2P
AIN2N
AIN1P
AIN1N
VBIAS
C15
0.1µF
C2
10µF
21
C9
1µF
U3
REF1004
20
XOUT
XIN
MODE
DRDY
SDOUT
SDIO
REFIN
REFOUT
SCLK
DSYNC
CS
DVDD
DGND
11
10
18
17
16
15
14
9
8
13
12
ADS1211
FIGURE 4. This is the recommended external reference circuit for the ADS1210 and ADS1211 when an effective resolution
of 23 bits rms is required.
4
of 1, and decimation ratio of 195 giving a data rate of 100Hz.
The average output of this data (referred to voltage input) is
43µV with a standard deviation of 32µVrms. The expected
performance of the ADS1211 in this configuration is
1.4µVrms, per Table II. The data in Figure 7 is taken from
the same device with a slight variation in the layout. The
length of the converter input leads is changed from six
inches to one inch.
the leads from the input sources as short as possible. This is
done to avoid EMI effects that could be coupled into the
inputs pins of the converter. A 0.1µF capacitor should be
placed directly across the differential inputs. This is done to
attenuate high frequency noise that is present at the input
pins of the device. The third noise reduction technique is to
insert an anti-aliasing filter on each analog input pin. This is
recommended to reduce high frequency out of band noise
from entering the converter and aliasing into the digital
output signal.
When testing these noise reductions techniques, the user
should be aware of a specific type of device noise that is
shown in Figure 5. This type of noise is known to exist in
converters using the ∆Σ topology. Certain low voltage inputs
create a low level rms noise at the output of the A/D
converter. These outputs seem to have a low frequency
component or tone.
ADS1210
TURBO 16, PGA 1, DR 3125, 100Hz, VIN = 0V
1.00E
0.00E
One Tenth Volts
–1.00E
RMS NOISE vs INPUT VOLTAGE LEVEL
(60Hz Data Rate)
–2.00E
–3.00E
–4.00E
–5.00E
–6.00E
–7.00E
2.5
–8.00E
RMS Noise (ppm)
–9.00E
1
2.0
51
101
151
201
251
Samples
1.5
FIGURE 6. The peaks shown in Figure 4 have a very low
frequency content. The frequency and magnitude of these
tones changes with layout and A/D converter programming
of turbo mode and data rate. This data was taken with the a
XIN of 10MHz, PGA of 1, decimation ratio of 195 and a
turbo mode of one.
1.0
0.5
–5.0 –4.0 –3.0 –2.0 –1.0
0
1.0
2.0
3.0
4.0
5.0
Analog Input Differential Voltage (V)
FIGURE 5. The noise shown in this graph is only apparent
after the noise levels of the ADS1210 and ADS1211 conversion process has been reduced through techniques discussed
in this application. These techniques include proper programming of the modulator, proper data rates, and proper
power plane layout.
ADS1210
TURBO 16, PGA 1, DR 3125, 100Hz, SMALL INPUT
–2.22E
One Tenth Volts
–2.24E
The tones originate when the modulator output is
10101010...or 110110110... or 001001001001, etc. That is,
the modulator output is a very short sequence of 1s and 0s
that repeat very often. This produces digital numbers in the
digital filter that are close to a “major” bit transition (such as
0111111... 1000000...). Every so often, the modulator output
skips a sequence. For example, 10101010 becomes 10010101.
This occasional skip seems to come along at a very low
frequency. Thus, the digital filter “believes” that there is
actually a low-level signal there.
–2.26E
–2.28E
–2.30E
–2.32E
–2.34E
–2.36E
1
51
101
151
201
251
Samples
FIGURE 7. This data is taken from the same device in the
same conditions as in Figure 5 with a slight variation in the
layout. The length of the input leads is changed from six
inches to one inch.
An example of this idle tone is shown in Figure 6. These
tones are very difficult to find and are usually the last issue
to deal with when trying to obtain 23 bits rms of effective
resolution. In the example in Figure 6, the A/D converter,
ADS1211, is configure in a PGA gain of one, Turbo mode
5
converter should be configured in a Turbo Mode of 16 and
data rates from to 10Hz to 60Hz. The analog and digital
power and grounds should be carefully separated for optimal
performance. A crystal oscillator is recommended, although,
clock oscillators can be used with great care. An external
reference is also recommended if 23 bits rms is the desired
effective resolution. The analog input leads to the input of
the A/D converter must be a short as possible and properly
filtered.
Also, note that the characteristics of the tone is dependent on the layout of the ADS1210/11. We have taken
an ADS1210/11 out of the demonstration board socket
(DEM-ADS1210/11), plugged it back in, and seen a change
in the oscillation amplitude and frequency. A soldered part,
particularly a surface mount part, should have smaller idle
tones and better performance.
Another way to reduce the idle tone problem is to introduce
a small offset voltage to the signal. As illustrated in Figure
5, a small offset voltage can take the converter away from
the sensitive input voltages that cause the problem.
REFERENCES
(1) Ryan, Scranton, “DC Amplifier Noise Revisited”, Analog Devices,
Analog Dialogue, 1984, pg 18-1.
CONCLUSION
(2) “ADS1210, ADS1211, 24-bit Analog-to-Digital Converter”, Product
Data Sheet PDS-1248, Burr-Brown Corporation.
The short cut to 23 bits rms of effective resolution with the
ADS1210 and ADS1211 gives attention to optimizing the
converter’s programming, circuit layout, a proper clock
source, and special care with the analog input pins. The
6
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