Hardware/Software Codesign I

Transcription

Professur Technische Informatik
Prof. Dr. Wolfram Hardt
System Development –
Models and Methods
Prof.
o Dr. Wolfram
o a Hardt
a dt
Dipl.-Inf. Mirko Caspar
Wintersemester 2010/11
Version: 10.02.L.r-1.0-100929
Contents
• HW/SW Codesign
C d i
Process
P
• Design Abstraction and Views
• Synthesis
• Control/Data-Flow
Control/Data Flow Models
• System Synthesis Models
CO
mplex
ncurrent
rrect
ordinated
DESIGN
02-2
1
Designing Embedded Systems
• design structuring
– representation of requirements
– necessary for automation of design process
design partitioning
• ________________________
– chip - chip
– board – board
– hardware – software
objects
algorithms
• design steps
– scheduling
– allocation
– binding
for HW and SW
02-3
HW/SW Codesign Process
Specification
System Synthesis
InterfaceSynthesis
SW Synthesis
y
machine code
____________
Estimation
HW Synthesis
y
netlist
02-4
2
Contents
• HW/SW Codesign
C d i
Process
P
• Synthesis
• System-Synthesis Models
CO
mplex
ncurrent
rrect
ordinated
DESIGN
02-5
Y-Chart
Behavioural
View
Synthesis
Structural
View
Test
View
 X-Chart
Physical
View
02-6
3
Example
• device: MP3 decoder ASIC (HW)
Behavioural View
Structural View
system
decode files with 32…256kBit,
32 Bit output quality, …
components for sample
detection, configurable decoder,
output registers
algorithm
description for each part, e.g. in
C / Java
detailed structure for different
parts of system
registertransfer
complex modules and their data
flow / communication
register-transfer components
and connections
gate
flip-flops, signals
Boolean
equation, FSM gates,
__________________________
__________________________
transistor
differential equations
transistors, resistors, wires, …
02-7
Double-Roof-Model
• abstraction of Y/X-chart
software
hardware
behaviour
___________
system
module
architecture
block
logic
 HW and SW design processes are equally structured
___________
structure
02-8
4
P-Chart
• dimension
– SW-Synthesis
– …
• level
–
–
–
–
system level
algorithm level
RT level
…
• view
–
–
–
–
behaviour
structure
test
geometry
02-9
Contents
• HW/SW Codesign
C d i
Process
P
• Synthesis
CO
mplex
ncurrent
rrect
ordinated
DESIGN
02-10
5
Synthesis
software
hardware
behaviour
system
y
module
architecture
block
logic
structure
• synthesis = _________________________
behaviour -> structure
• tasks for synthesis:
– allocation:
– binding:
– scheduling:
select components
map functions to components
plan execution order
02-11
Example
• behaviour:
Boolean equation
f  ab  cd
synthesis
• structure:
netlist
a
b
&
≥1
f
c
d
&
02-12
6
Specification on System Level
constraints
A
task graph
B
C
execution time
< 200ms
D
E
02-13
Allocation on System Level
• processor, dedicated hardware
• memory, I/O
• connection structures
02-14
7
Binding on System Level
• map tasks to resources
A
B
C
D
E
02-15
Scheduling on System Level
02-16
8
Rating of Design Alternatives
pareto point
_______________:
criteria can not be
improved without worsen
another
pareto points
 1, 2, 4, 6 are ___________
02-17
Contents
• HW/SW Codesign
C d i
Process
P
• Synthesis
CO
mplex
ncurrent
rrect
ordinated
DESIGN
02-18
9
Data Structures
• ffor algorithms
l
ith
((calculation
l l ti
off optimisations)
ti i ti
) are d
dedicated
di t d and
d
formal models necessary  data structures
• granularity
– detailing for optimisation parameters
– abstraction for manageability
• extendibility
– annotation by optimisation method
– output generation, if necessary for common optimisation
02-19
Graph
• modelling by graphs
– graph G = (V
(V,E),
E) E ‫ ك‬V x V
set of vertices (nodes) V:
operation, tasks, communication
set of arcs (edges)
dependencies between nodes
E:
A
• example:
– G = ((V,E))
– V = (A, B, C, D, E)
– E = ((A,B), (A,C), (B,E), (C,D), (D,E))
– directed graph (A,B) ֙(B,A)
B
C
D
E
02-20
10
Control and Data Flow Models
• possible
ibl dependencies
d
d
i to
t model
d l by
b d
data
t structure
t
t
– data dependency
– control dependency
resource conflicts
– ____________________
(caused by implementation)
• important models
– data flow graph (DFG)
– control flow graph (CFG)
– system modelling graphs (later)
02-21
Data Flow Graph (DFG)
• shows data dependencies between calculation or memory units
(functions, variables, ALUs, …)
• directed edge,
edge if a producer-consumer
producer consumer relation between two
nodes
x = 3*a + b*b – c;
y = a + b*x;
z = b – cc*(a
(a + b);
02-22
11
Control Flow Graph (CFG)
• models control paths of algorithms
• directed graph with one start and
one end node
foo
{ read(a,b);
done = false;
repeat
{
if (a > b)
a = a – b;
else
if (b > a)
b = b – a;
else done = true;
} until done;
write(a);
}
start
instructions
read(a,b)
done = FALSE
branch
a > b
a = a-b
b > a
b = b-a
true
false
done = TRUE
done != TRUE
write(a)
end
02-23
Contents
• HW/SW Codesign
C d i
Process
P
• Synthesis
CO
mplex
ncurrent
rrect
ordinated
DESIGN
02-24
12
Models for System Synthesis
• problem graph
– nodes:
nodes
– edges:
ffunctional
nctional and communication
comm nication objects
dependencies
• architecture graph
– nodes:
– edges:
functional and communication resources
directed communication paths
• specification graph
possible mapping
– problem graph + architecture graph + ___________________
02-25
Problem Graph
1
2
1
2
5
3
3
6
7
4
DFG
communication nodes
4
problem graph
02-26
13
Architecture Graph
architecture
architecture graph
RISC
RISC
bus
bus
FPGA1
FPGA1
FPGA2
P2P
point-to-point link
communication resources
FPGA2
02-27
Specification Graph
weighting (different scenarios)
1
2
10 | 7 | 100
RISC
1|1|5
5
3
6
5 | 3 | 100
bus
FPGA1
P2P
7
FPGA2
4
problem graph
possible mapping
architecture graph
specification graph
02-28
14
Example
• HW/SW partitioning (__________________)
bi-partitioning
HW
HW
bus
bus
processor
processor
architecture
architecture graph
 only two blocks (HW and SW)
02-29
15

Hardware/Software Codesign I

Transcription

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