DSF Quartus II
Transcription
DSF Quartus II
Digitale Signalverarbeitung mit FPGA Digitale Signalverarbeitung mit FPGA (DSF) Quartus II Stand: Mai 2007 Jens Onno Krah Cologne University of Applied Sciences www.fh-koeln.de [email protected] Quartus II 1 Digitale Signalverarbeitung mit FPGA Quartus II Software Design Series : Foundation © 2007 Altera Corporation Quartus II - Krah SS 2007 Digitale Signalverarbeitung mit FPGA The Programmable Solutions Company® Programmable Logic Devices Tools − − − − Quartus® II software SOPC Builder DSP Builder Nios® II IDE Intellectual Property (IP) − Signal processing − Communications − Embedded processors Nios II embedded processor Quartus II 3 Digitale Signalverarbeitung mit FPGA Programmable Logic Families Structured ASIC − HardCopy® II & HardCopy Stratix devices High & medium density FPGAs − Stratix® III, Stratix lI & Stratix devices Low-cost FPGAs − Cyclone® II & Cyclone devices FPGAs w/ clock data recovery − Stratix II GX & Stratix GX devices CPLDs − MAX® II, MAX 7000 & MAX 3000 devices Configuration devices − Serial (EPCS) & enhanced (EPC) Quartus II 4 Digitale Signalverarbeitung mit FPGA Quartus II - Krah SS 2007 Digitale Signalverarbeitung mit FPGA Software & Development Tools Quartus II Subscription Edition − Stratix III, Stratix II & Stratix devices − Stratix II GX & Stratix GX devices − Cyclone II & Cyclone devices − HardCopy II & HardCopy Stratix devices − MAX II, MAX 7000S/AE/B, MAX 3000A devices − Select older families Quartus II Web Edition − Free version − Not all features & devices included See www.altera.com for feature comparison Quartus II 5 Digitale Signalverarbeitung mit FPGA Quartus II Design Software Fully-integrated development tool − Multiple design entry methods − Logic synthesis − Place & route − Simulation − Timing & power analysis − Device programming Quartus II 6 Digitale Signalverarbeitung mit FPGA Quartus II - Krah SS 2007 Digitale Signalverarbeitung mit FPGA More Features − MegaWizard® & SOPC Builder design tools − TimeQuest Timing Analyzer − Incremental Compilation feature − PowerPlay Power Analyzer tool − NativeLink® 3rd-party EDA tool integration − Debugging capabilities From HDL to device in-system − 32 & 64-bit Windows, Solaris, & Linux support − Multi-processor support − Node-locked & network licensing options Quartus II 7 Digitale Signalverarbeitung mit FPGA Quartus II Operating Environment Project Navigator Status window Message window Quartus II 8 Digitale Signalverarbeitung mit FPGA Quartus II - Krah SS 2007 Digitale Signalverarbeitung mit FPGA Typical PLD Design Flow Design entry/RTL coding Design Specification - Behavioral or structural description of design RTL simulation - Functional simulation (ModelSim®, Quartus II) - Verify logic model & data flow (no timing delays) LE M512 M4K I/O Synthesis - Translate design into device specific primitives - Optimization to meet required area & performance constraints - Quartus II, Precision Synthesis, Synplify/Synplify Pro, Design Compiler FPGA Place & route - Map primitives to specific locations inside Target technology with reference to area & performance constraints - Specify routing resources to be used Quartus II 9 Digitale Signalverarbeitung mit FPGA Typical PLD Design Flow Timing analysis tclk - Verify performance specifications were met - Static timing analysis Gate level simulation - Timing simulation - Verify design will work in target technology PC board simulation & test - Simulate board design - Program & test device on board - Use SignalTap II for debugging Quartus II 10 Digitale Signalverarbeitung mit FPGA Quartus II - Krah SS 2007 Digitale Signalverarbeitung mit FPGA Quartus II Projects Description − Collection of related design files & libraries − Must have a designated top-level entity − Target a single device − Store settings in Quartus II Settings File (.QSF) Create new projects with New Project Wizard − Can be created using Tcl scripts Quartus II 11 Digitale Signalverarbeitung mit FPGA Design Entry Methods Quartus II − Text Editor AHDL VHDL Verilog − Schematic Editor Block diagram file Graphic design file − Memory Editor HEX MIF Top-level design files can be schematic, HDL or 3rd-Party Topnetlist file Level File .bdf .gdf .bsf .tdf .vhd .v .edf .edif .v, vlg, .vhd, .VHDL, vqm Block file Symbol file Text file Text file Text file Text file Text file 3rd-party EDA tools Generated within Quartus II − EDIF 2 0 0 − Verilog Quartus Mapping (.VQM) Mixing & matching design files allowed Quartus II 12 Digitale Signalverarbeitung mit FPGA Quartus II - Krah SS 2007 Imported from 3rd-Party EDA tools Digitale Signalverarbeitung mit FPGA Text Design Entry Quartus II Text Editor features − Block Commenting − Line numbering in the HDL text files − Preview of HDL templates − Syntax coloring − Edited but unsaved filenames appear with an asterisk (*) next to the filename in the GUI Enter text description − AHDL (.TDF) − VHDL (.VHD, .VHDL) − Verilog (.V, .VLG, .Verilog, .VH) Quartus II 13 Digitale Signalverarbeitung mit FPGA Verilog & VHDL VHDL- VHSIC hardware description language − IEEE Std 1076 (1987 & 1993) supported − IEEE Std 1076.3 (1997) synthesis packages supported Verilog − IEEE Std 1364 (1995 & 2001) & 1800 (SystemVerilog) supported Create in Quartus II or any standard text editor Use Quartus II integrated synthesis to synthesize View supported commands in on-line help Learn more about HDL in Altera HDL Customer Training Classes Quartus II 14 Digitale Signalverarbeitung mit FPGA Quartus II - Krah SS 2007 Digitale Signalverarbeitung mit FPGA AHDL Altera hardware description language − High-level hardware behavior description language − Used in Altera megafunctions − Uses boolean equations, arithmetic operators, truth tables, conditional statements, etc. Create in Quartus II or any standard text editor Quartus II 15 Digitale Signalverarbeitung mit FPGA HDL Templates 2) Select language 3) Select template section 1) Click on toolbar shortcut or Insert Template (Edit Menu) Quartus II 16 Digitale Signalverarbeitung mit FPGA Quartus II - Krah SS 2007 4) Preview window display section Digitale Signalverarbeitung mit FPGA Schematic Design Entry Full-featured schematic design capability Schematic design creation − Draw schematics using library functions (blocks) Gates, flip-flops, pins & other primitives Altera megafunctions & LPMs − Create symbols for Verilog, VHDL, or AHDL design files − Connect all blocks using wires & busses Quartus II 17 Digitale Signalverarbeitung mit FPGA Create Schematic Use the Quick Link or File ⇒ New ⇒ Schematic File Quartus II 18 Digitale Signalverarbeitung mit FPGA Quartus II - Krah SS 2007 File Extension Is .BDF Digitale Signalverarbeitung mit FPGA Insert Symbols Open the Symbol Window: Use the Toolbar or Double Click Schematic Background Local Symbols Created from MegaWizard or Design Files Library Symbols Quartus II 19 Digitale Signalverarbeitung mit FPGA Connect Wires & Buses Draw Wires, Buses, or Conduit Quartus II 20 Digitale Signalverarbeitung mit FPGA Quartus II - Krah SS 2007 Digitale Signalverarbeitung mit FPGA Change Names & Properties Double-Click on Pin Name to Change; Hit Enter to Advance to Next Pin Right-Click on any Block to Change Properties (Ex. Instance Name) Quartus II 21 Digitale Signalverarbeitung mit FPGA Create Symbols Converted schematic to a Symbol to be used in other schematic files Symbol Created in Project Directory File ⇒ Create/Update ⇒ Create Symbol… Quartus II 22 Digitale Signalverarbeitung mit FPGA Quartus II - Krah SS 2007 Digitale Signalverarbeitung mit FPGA Altera Megafunctions Pre-made design blocks Benefits − Configurable settings add flexibility − “Drop-in” support to accelerate design entry − Pre-optimized for Altera architecture Two versions − Quartus II megafunctions − Intellectual Property (IP) megafunctions Quartus II 23 Digitale Signalverarbeitung mit FPGA IP Megafunctions Must purchase license to use in finished design Two types − Logic for IP function is encrypted − MegaCore® IP Developed by Altera Install with Quartus II software or download/install individually from www.altera.com − Altera Megafunctions Partner Program (AMPP℠) IP Developed by 3rd-Party IP vendors & certified by Altera Contact vendor for evaluating and licensing function All MegaCore functions & some AMPP functions support OpenCore® Plus feature − Develop design using free version of core − HDL simulation models provided with IP − Generate time-limited configuration/programming files Quartus II 24 Digitale Signalverarbeitung mit FPGA Quartus II - Krah SS 2007 Digitale Signalverarbeitung mit FPGA Example MegaCore IP Triple-Speed Ethernet MAC FIR Compiler Fast Fourier Transform DDR2 Memory Controller CRC Compiler PCI Compiler Quartus II 25 Digitale Signalverarbeitung mit FPGA Assignment Editor (AE) Provides spreadsheet assignment entry & display − Can copy & paste from clipboard Assignments Menu Enable/disable individual assignments Sort on columns Assignment Editor toolbar Quartus II 26 Digitale Signalverarbeitung mit FPGA Quartus II - Krah SS 2007 Customizable columns Digitale Signalverarbeitung mit FPGA Quartus II Full Compilation Flow* Design Files Analysis & Elaboration Constraints & Settings Synthesis Constraints & Settings Fitter Functional Simulation Functional Netlist Assembler Programming & Configuration files (.sof/.pof) TimeQuest Timing Analysis Gate-Level Simulation EDA Netlist Writer *This is the typical flow. Other module executables will be added if additional software features are enabled. Quartus II 27 Digitale Signalverarbeitung mit FPGA Quartus II - Krah SS 2007 Post-Fit Simulation Files (.vho/.vo)