IHP Im Technologiepark 25 15236 Frankfurt (Oder) Germany

Transcription

Practical Aspects of Testing
Based on Experiences with Verigy 93000 SOC
Wolf, Christoph
IHP
Im Technologiepark 25
15236 Frankfurt (Oder)
Germany
www.ihp-microelectronics.com
© 2007 - All rights reserved
Outline
•
Introduction
•
Tester architecture concepts
•
Test pattern generation/conversion
•
Event-based test system
•
Memory test
•
Limitations of standard test systems
Usage Scenarios
•
Standalone
Manual test of packaged devices
•
Docked to a handler
Automatic test of packaged devices
Usage Scenarios
•
Docked to a wafer prober
Automatic test of unpackaged devices directly on a wafer
Typical Tester Architecture
•
Basic infrastructure
Manipulator
Test system power supply
Clock- and control boards
Cooling
Air or liquid
•
(Test) Application specific equipment
Device power supply
General purpose, high voltage, high current, low noise, multi-channel
Digital channels
Analog & RF-resources
Waveform generators, digitizers, TIAs
Utility lines (external circuitry, relay control, etc.)
Tester Architecture
•
•
Central control
Central resources (control, memory etc) → distributed to channels
Advantage:
Simpler system architecture, lower complexity
„Tester-per-pin“-architecture
Mostly used in modern high performance testers
(Nearly) all resources available separately for each channel
Advantage:
Higher throughput possible (e.g. no memory bottleneck)
Increased flexibility (multi-port and/or multi-site capabilities)
Test Program Implementation Styles
•
Different implementation schemes varying among vendors and tester
families
Standard programming languages (C,…)
Specialized script-like high level languages
GUI-based approaches (“graphical programming” by joining basic
building blocks)
•
Example Agilent/Verigy 93000 SOC
Testvsystem based on extensive set of firmware commands
Several editors (both pure text editors and custom windows)
Majority of data stored as text files, partly embedded firmware commands
Vectors stored in binary format
Built-in test functions
API for customer specific tasks in C++
Test Program Entities
•
Typical set of common basic entities
Pin configuration: map logical pin/signal names to physical tester
resources
Level configuration: voltages to apply to the chip and compare
against
Timing configuration: define when signal events should occur
Vector configuration: actual data to be applied to the chip
Tests: continuity test, functional test, memory test, static/dynamic
current, …
Testflow: sequence of tests
External interfaces: prober/handler control, data logging
Pin Electronics – General Principle
Clamps
Vih
Driver
(Input)
DUT
0
ZL=50O
50O
Vcc1
1
2
Vil
3
a1
b1
a2
b2
a3
b3
a4
b4
5
6
7
Voh
4
Receiver
(Output)
8
GND
0
PPMU
Vol
Iol
Active Load
50O
Vt
Ioh
Pin Electronics – Driver Mode
Driver
(Input)
Clamps
Vih
DUT
TristateCtrl
0
ZL=50O
50O
Vcc1
1
a1
b1
a2
b2
a3
b3
a4
b4
5
Formatted
Data
2
Vil
3
4
6
7
8
GND
Voh
0
Receiver
(Output)
PPMU
Vol
Iol
Active Load
50O
Vt
Ioh
Pin Electronics – Receiver Mode
Driver
(Input)
Clamps
Vih
DUT
TristateCtrl
0
ZL=50O
50O
Vcc1
1
a1
b1
a2
b2
a3
b3
a4
b4
5
Formatted
Data
2
Vt
Vil
3
4
6
7
8
GND
Receiver
(Output)
Voh
0
> Voh
PPMU
< Vol
Vol
Iol
Active Load
50O
Vt
Ioh
Waveform Generation
•
ATE systems typically strictly cycle-based
No instantaneous change of cycle period during pattern execution
•
Fixed format based approach
Fixed set of available waveforms
(D)NRZ (delayed non-return to zero)
RZ, RO (return to zero/one)
SBC (surrounded by complement)
STB (edge strobe)
WSTB (window strobe)
0
1
Timing setup defines edge positions
Vector setup defines data (logical 0/1)
Waveform type can be per pin or per cycle
Waveform Generation
•
Flexible waveform setup (93k style)
Wavetable defines (up to 256) different waveform shapes
Combination of max 8 drive and 8 receive edges
Pure shape definition, only edge actions (drive 0/1/Z, strobe L/H/X), no timing
Equations define edge positions in time, no shape/action information
Specset joins one wavetable and one equation set, optional spec vars
Vectors do not contain logical values but indices into wavetable
Test references a spec set (defines timing+wavetable) + vector set
Flexible combinations of vector, timing and waveform shape sets possible
Example:
Basic functional test with NRZ waveforms
Characterization tests (setup/hold time) with SBC waveforms
Setup Example
•
Wavetable
0 d1:0
1 d1:1
2 d4:1 d6:0
3 d2:1 d3:0 d4:1 d5:0
4 d2:Z r1:H r2:L
5 d2:Z r1:L r2:L
0
45
Equations
period=45
d1=0
d2=5
d3=10
d4=20
d5=25
d6=40
r1=30
r2=40
90
Vector
0
2
3
1
4
135
180
225
H
0
2
3
1
4
L
X-Modes
•
Complex wavetables enable vector compression (or higher data rate)
Several (device) cycles encoded into one tester cycle
Limited by number of distinct edges and wavetable count
Examples (Verigy 93000, 8 driving + 8 receiving edges, 256 waveforms)
Data input NRZ (1 edge, 0/1)
→ 8 edges, 2^8 = 256 states ⇒ x8
Clock signal RZ (2 edges, 0/1) → 2x4 edges, 2^4 states
Bidir pin NRZ/STB (0,1,L,H)
⇒ max x4
→ 4 edges, 4^4=256 states
⇒ max x4
Bidir pin NRZ/STB (0,1,L,H,X) → 4 edges, 5^4 > 256 states ⇒ max x3
High(er) Speed Testing Issues
•
Signal reflections in unmatched environments
Driver can be used to supply 50Ω termination in receiver mode
Third level termination or active load for bidirectional pins
Device must be able to drive into 50Ω
For CMOS devices usually not fulfilled → impedance matching
resistors required on the load board
Termination acts as voltage divider → only reduced levels seen by
tester
High(er) Speed Testing Issues
•
Fixture delay calibration
Considerable signal propagation times from tester electronics to DUT
Tester calibrated up to fixed interface, additional delays on DUT board
TDR measurement to determine additional propagation time
Input signals are applied earlier, output signals are evaluated later
Tester-Side
-td
0
DUT-Side
+td
-td
0
+td
t
Input
Output
Works fine for unidirectional pins, problems with bi-directional pins
Solution: separate tester channels for input and output path
Test Pattern Generation/Conversion
•
•
Several test program elements can be generated by hand
Test vectors usually require automatic handling
•
Example Verigy 93000
Direct creation of binary vector files by appropriate tools
Import of already cyclized text format data via „ascii interface“
Device cycle file: list of state characters and corresponding waveforms
Pins clock
DVC df
0
0:0ns
1
1:0ns
P
1:10ns
0:20ns
ASCII vector file: one vector per row, one state character per pin
Each line holds data of one tester cycle
•
Two major sources of test patterns
Structural test patterns generated by ATPG tools
Design data required, tests for specific faults
Mostly used in combination with scan chains to reduce complexity
Usually used for production test to verify defect-free fabrication
Higher effort to catch timing-related issues
Usually generated already in cycle based format (WGL, STIL)
Functional test patterns
Blackbox testing
Knowledge about internal structure not
necessarily required
Often used for design verification
Mostly generated by simulation
•
Functional tests at IHP
No product development and no mass production
High rate of new designs in prototype state
Transition to structural tests but functional test still dominant
•
Functional test patterns obtained by logging simulation runs
Problem: simulation is event-based, usually (e)vcd file format for export
Events can occur at arbitrary positions
(E)VCD: (extended) value change dump format
•
(E)VCD state characters
VCD: 0/1/X/Z
Additional direction control signals for bi-directional pins required
EVCD: D/U/N/Z/d/u; L/H/X/T/l/h; extra state characters for collisions
Signal direction encoded into state characters, no need for separate
direction control signals
Strength encoding: 0-6, separately for low and high value
•
(E)VCD file format
header (version info, timescale)
signal declaration list (including hierarchy)
initialization dump
time stamp
event list
time stamp
event list
...
Test Pattern Generation/Conversion – EVCD example
$var port
$var port
$var port
$var port
#0
pD 6 0 <1
pD 6 0 <2
pD 6 0 <4
pX 0 0 <3
#45
pU 0 6 <2
pZ 0 0 <4
#50
pU 0 6 <1
#71
pH 0 6 <3
#100
pD 6 0 <1
#150
pU 0 6 <1
#154
pL 6 0 <4
#200
pD 6 0 <1
#3450
pU 0 6 <1
#3454
pH 0 6 <4
1
1
1
1
<1
<2
<3
<4
Clk $end
In $end
Out $end
Inout $end
0
50
100
150
200
250
...
3450
Clk
In
Out
XXXXXXXX
i
Inout
o
•
Required processing: cyclization
Event file partitioned into cycles of equal length
Optional signal conditioning (scaling, shifting events, ...)
Potentially long periods of inactivity → event based format does not
contain data; cycle based format requires data for each cycle
Two methods for waveform mapping:
Signal sampling at specified positions, acquired value is taken as
argument for the parameterized tester waveform
Advantage: relatively simple process
Disadvantages:
Only one value acquired
Multiple signal changes in a single cycle ignored/not detected
Careful selection of sample point required if signal changes
occur at different positions with respect to the cycle
Matching with predefined match waveforms, selection of
corresponding target waveform
Disadvantage: computing intensive
Advantages:
More complex waveforms can be reproduced
Implicit cross check of simulation against a set of predefined
waveforms
General problem:
Arbitrary event based waveform must be reduced to cycle based
representation with strictly limited number of signal changes (i.e.
timing edges)
Event-Based Test System
•
Advantest CertiMAX
Inherently event based: test data stored as events
(Action, time offset from previous event)
System can directly read evcd files, no cyclization
Each channel can run completely independently
from each other
Single events can be repositioned
Minimum time 8ns between events
Limited speed but very suitable for functional
debugging
Memory test
•
Several different algorithms
Solid, Checkerboard, March, ...
•
Differentiation between device address, physical address and
topological address
Device address: externally applied address
Physical address: internal address (x,y,d)
Topological address: internal addres (x,y)
•
Scrambling
Relation between device & physical address
Memory test algorithms deal with cell neighborship → calculate
device address such that physical addresses match algorithm
•
Bitmap centric view rather than cycle based view
Mapping between physical and topological addresses
Memory Test – Scrambling Example
0,0
127
A[14..8]
0
0
A[14..8]
0
A[7..0]
A[16:15]=00
01
Address range split into row (y) and
column (x) addresses
ya[8..0] = A[16] A[7..0]
xa[7..0] = A[15] A[14..8]
255
(A[16:15] „block address“, prepended
to x and y base addresses)
255
10
A[7..0]
127
0
11
ya/xa: externally applied device addr.
y/x: internal physical addr.
Scrambling: equations to calculate external addresses based on internal physical
addresses such that x increases to the right and y increases to the bottom
xor used as conditional inversion (mirror base address depending on block address)
ya[7:0] = y[7..0] XOR y[8]
ya[8] = y[8]
xa[6:0] = x[6..0] XOR NOTx[7]
xa[7] = x[7]
Memory Test – Algorithmic Pattern Generation (APG)
•
Memory tests can have high complexity (>6N)
•
Huge amount of vectors for large memories
•
AGPs compute vectors on the fly rather than storing them
Make use of high regularity of memory tests
→ Loop and repeat constructs, memory test algorithms implemented as
sequencer programs
Example: solid test (write complete memory, read complete memory, n words)
LSB: 01010101...
00110011...
MSB: 0000...1111
→ rep (2 * rep (n/2) * „01“)
→ rep (2 * rep (n/4) * “0011“)
→ rep (2 * (rep (n/2)*“0“, rep (n/2)*“1“))
Limitations of Standard Test Systems
•
Speed, vector memory
•
Number of distinct timing edges
•
Number of independent clock domains
Despite tester-per-pin architecture usually common master clock, no
truly asynchronous signals possible
•
Very limited degree of flexibility on pattern level
Match loop: loop around until chip output matches the loop vector
(i.e. for flash testing or PLL locking)
No further (conditional) processing on vector level
⇒ Severe problems with respect to asynchronous circuits

IHP Im Technologiepark 25 15236 Frankfurt (Oder) Germany

Transcription

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